Host Interface Signals - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

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Host Interface Signals

Note: Unless otherwise noted, the voltage level for all signals in this interface is tied to the termination
voltage of the Host Bus (V
Signal Name
HADS#
HBNR#
HBPRI#
HBREQ0#
HCPURST#
HDBSY#
HDEFER#
HDINV[3:0]#
®
Intel 82925X/82925XE MCH Datasheet
).
TT
Type
I/O Address Strobe: The processor bus owner asserts HADS# to indicate the
first of two cycles of a request phase. The MCH can assert this signal for
GTL+
snoop cycles and interrupt messages.
I/O Block Next Request: This signal is used to block the current request bus
owner from issuing new requests. This signal is used to dynamically control
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the processor bus pipeline depth.
O Priority Agent Bus Request: The MCH is the only Priority Agent on the
processor bus. It asserts this signal to obtain the ownership of the address
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bus. This signal has priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions unless the
HLOCK# signal was asserted.
I/O Bus Request 0: The MCH pulls the processor's bus HBREQ0# signal low
during HCPURST#. The processor samples this signal on the active-to-
GTL+
inactive transition of HCPURST#. The minimum setup time for this signal is
4 HCLKs. The minimum hold time is 2 clocks and the maximum hold time is
20 HCLKs. HBREQ0# should be tri-stated after the hold time requirement
has been satisfied.
O CPU Reset: The HCPURST# pin is an output from the MCH. The MCH
asserts HCPURST# while RSTIN# is asserted and for approximately 1 ms
GTL+
after RSTIN# is de-asserted. The HCPURST# allows the processors to
begin execution in a known state.
®
Note that the Intel
up and hold times around HCPURST#. This requires strict synchronization
between MCH HCPURST# de-assertion and the Intel® ICH6 driving the
straps.
I/O Data Bus Busy: This signal is used by the data bus owner to hold the data
bus for transfers requiring more than one cycle.
GTL+
O Defer: Signals that the MCH will terminate the transaction currently being
snooped with either a deferred response or with a retry response.
GTL+
I/O Dynamic Bus Inversion: Driven along with the HD[63:0] signals. Indicates
if the associated signals are inverted or not. HDINV[3:0]# are asserted such
GTL+
that the number of data bits driven electrically low (low voltage) within the
corresponding 16 bit group never exceeds 8.
HDINVx#
HDINV3#
HDINV2#
HDINV1#
HDINV0#
Description
ICH6 must provide processor frequency select strap set-
Data Bits
HD[63:48]
HD[47:32]
HD[31:16]
HD[15:0]
Signal Description
23