Pcicmd-Pci Command (D0:F0) - Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Datasheet

R
4.1.3 PCICMD—PCI Command (D0:F0)
PCI Device:
Address Offset:
Default Value:
Access:
Size:
Since MCH Device 0 does not physically reside on Primary PCI bus, many of the bits are not
implemented.
Bit
15:10
9
8
7
6
5
4
3
2
1
0
®
Intel 82925X/82925XE MCH Datasheet
Access &
Default
Reserved
RO Fast Back-to-Back Enable (FB2B). This bit controls whether or not the master
0b can do fast back-to-back write. Since device 0 is strictly a target this bit is not
implemented and is hardwired to 0.
R/W SERR Enable (SERRE). This bit is a global enable bit for Device 0 SERR
0b messaging. The MCH does not have a SERR signal. The MCH communicates
the SERR condition by sending an SERR message over DMI to the ICH6.
1 = Enable. The MCH is enabled to generate SERR messages over DMI for
specific Device 0 error conditions that are individually enabled in the
ERRCMD register. The error status is reported in the ERRSTS, and PCISTS
registers. If SERRE is clear, then the SERR message is not generated by the
MCH for Device 0.
0 = Disable
Note: That this bit only controls SERR messaging for the Device 0. Device 1 has
its own SERRE bits to control error reporting for error conditions occurring in that
device. The control bits are used in a logical OR manner to enable the SERR
DMI message mechanism.
RO Address/Data Stepping Enable (ADSTEP). Hardwired to 0.
0b
RO Parity Error Enable (PERRE). PERR# is not implemented by the MCH and this
0b bit is hardwired to 0.
RO VGA Palette Snoop Enable (VGASNOOP). Hardwired to a 0.
0b
RO Memory Write and Invalidate Enable (MWIE). The MCH will never issue
0b memory write and invalidate commands. This bit is therefore hardwired to 0.
RO Reserved
0b
RO Bus Master Enable (BME). The MCH is always enabled as a master. This bit is
1b hardwired to a 1.
RO Memory Access Enable (MAE). The MCH always allows access to main
1b memory. This bit is not implemented and is hardwired to 1.
RO I/O Access Enable (IOAE). Hardwired to a 0.
0b
Host Bridge/DRAM Controller Registers (D0:F0)
0
04h
0006h
RO, R/W
16 bits
Description
49