Pci Express* Gen 2; Enterprise South Bridge Interface (Esi) Features; Controller Link (M-Link); Management Engine (Me) - Intel E42249-003 Product Specification

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Intel Server Board S5500BC TPS
3.3.1

PCI Express* Gen 2

PCI Express* generation 1 and 2 are dual simplex, point-to-point serial differential low voltage
interconnect. The signaling bit rate is 2.5 Gbit/sec/lane/direction for Generation 1 and 5.0
Gbit/sec/lane/direction for Generation 2.
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The Intel S5500 chipset on the Intel
interface. The key features are the following:
 Connected to three PCI Express* Gen2 x8 connectors (one with x4 link).

Connected to 82574L GbE with a PCI Express Gen2 x1 link.
 Compliant with the PCI Express* 2.0 specification.
3.3.2

Enterprise South Bridge Interface (ESI) Features

The interface between the Intel
South Bridge Interface or simply ESI. ESI is electrically equivalent to the PCI Express*
Generation 1 interface and the routing guidelines are similar.
3.3.3

Controller Link (M-Link)

The Controller Link is the interconnect that connects the north bridge (IOH) to the LAN
Controller in the ICH. The Management Engine (ME) resides in the IOH and communicates with
the ICH LAN Controller through this interface.
3.3.4

Management Engine (ME)

The Management Engine (ME) is an embedded ARC controller within the IOH. The IOH ME
performs manageability functions called Intel
Baseboard Management Controller (BMC).
Server Platform Services are value-added platform management options that enhance the value
of Intel platforms and their component ingredients (CPUs, chipsets and I/O components). Each
service is designed to function independently wherever possible, or grouped together with one
or more features in flexible combinations to allow OEMs (Original Equipment Manufacturers) to
differentiate platforms. The following is a high-level view of the Intel
SPS functions.

Node Management Features:

NPTM Policy Manager
 Power Supply Monitoring Service
 Inlet Temperature Monitoring Service (support for this feature on Intel servers is
platform-specific)
 CPU Power Limiting Service

Provide Access to ICH10 Devices:
The ME has control of ICH10 platform instrumentation. SPS provides a mechanism for
the BMC to access this instrumentation through IPMI OEM commands. Use of this
capability on Intel servers is platform-/SKU-specific.
Revision 1.0
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Server Board S5500BC provides PCI Express* Gen2
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IOH 5500 chipset and Intel
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Server Platform Services (SPS) for the discrete
Intel order number: E42249-003
Functional Architecture
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ICH10R is called the Enterprise
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Server Board S5500BC
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