Figure 1-7. Mx2820 Multiplexer System Configuration; System Connectivity; Power Connections; Timing - ADTRAN MX2820 System Manual

SYSTEM CONNECTIVITY

The shelf backplane contains Input/Output (I/O) connectors, control and signal routing,
power input and ground, plus the interconnections between BITS clock cards, MUX cards,
and the SCU.
Figure 1-7 shows the MX2820 Multiplexer system with management and network interfaces.
VT100
Terminal
RS232
To
Subtended
Shelves

Figure 1-7. MX2820 Multiplexer System Configuration

Power Connections

The MX2820 system is designed to accommodate redundant power configurations. The
system operates with either individual supply or both supplies functioning. Dual terminals for
DC Voltage (–48 or ±24 VDC) and return are provided.
A Barrier strip connector on the shelf backplane provides the power connections for power
and the frame ground. The frame ground connection is routed to the metal MX2820 chassis.

Timing

The MX2820 system operates in local, loop (network), or external (BITS) timing mode. In the
local timing mode, an onboard timing reference is provided. In the loop timing mode, the MUX
modules synchronize with the received DS3 or STS-1 signal. Because the multiplexing/de-
multiplexing process is asynchronous, each DS1 channel maintains its own Transmit and
Receive timing.
External timing mode only applies to STS-1 MUX modules and requires an MX2820 Clock
module. The STS-1 MUX module synchronizes its STS-1 transmit signal to the DS1 BITS clock
signal received at the Clock module.
61186003L1-1D
SNMP Management
Station
NMA Mainframe
Ethernet
LAN
Network
10BaseT
RS485
Section 1, System Description - System Connectivity
DS3
STS-1
X.25
DSX-1 (T1/E1)
Built-in
PAD
BLANK
SCU MUX MUX MUX MUX
1186000 1186003 ACT 1186002 1186002 1186002 1186002
ALM
ACT ACT ACT ACT
ALM ALM ALM ALM
C
STAT STAT STAT STAT
R
A DS3 DS3 DS3
TEST TEST TEST TEST
F
T
CLK A STAT STAT STAT STAT
DS1 DS1 DS1
TEST TEST TEST TEST
BLANK
1186000
ACO
CLKB 1A 1B 2A 2B
Network
Network
Network
MX2820
MUX MUX MUX MUX MUX MUX MUX MUX MUX MUX MUX
1186002 1186002 1186002 1186002 1186002 1186002 1186002 1186002 1186002 1186002 1186002
ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT
ALM ALM ALM ALM ALM ALM ALM ALM ALM ALM ALM
STAT STAT STAT STAT STAT STAT STAT STAT STAT STAT STAT
DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3 DS3
TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST
STAT STAT STAT STAT STAT STAT STAT STAT STAT STAT STAT
DS1 DS1 DS1 DS1 DS1 DS1 DS1 DS1 DS1 DS1 DS1 DS1
TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST
3A 3B 4A 4B 5A 5B 6A 6B 7A 7B 7B
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