Analog Devices Advantiv ADV7619 Hardware User's Manual page 90

UG-237
The ISRC1 packet registers are considered valid if ISRC1_PCKT_RAW is set to 1.
ISRC1_PCKT_RAW , IO, Address 0x60[6] (Read Only)
Raw status signal of International Standard Recording Code 1 (ISRC1) packet detection signal.
Function
ISRC1_PCKT_RAW
0 (default)
1
Table 26. ISRC2 Packet Registers
InfoFrame Map Address
0xF5
0xF6
0xF7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
1
As defined by the HDMI 1.3 specifications.
The ISRC2 packet registers are considered valid if, and only, if ISRC1_PCKT_RAW is set to 1.
ISRC2_PCKT_RAW , IO, Address 0x60[7] (Read Only)
Raw status signal of International Standard Recording Code 2 (ISRC2) packet detection signal.
Function
ISRC2_PCKT_RAW
0 (default)
1
Description
No ISRC1 packets received since the last HDMI packet detection reset.
ISRC1 packets have been received. This bit resets to zero after an HDMI packet detection reset or
upon writing to ISRC1_PACKET_ID.
R/W Register Name
R/W ISRC2_PACKET_ID[7:0]
R ISRC2_HEADER1
R ISRC2_HEADER2
R ISRC2_PB_0_1
R ISRC2_PB_0_2
R ISRC2_PB_0_3
R ISRC2_PB_0_4
R ISRC2_PB_0_5
R ISRC2_PB_0_6
R ISRC2_PB_0_7
R ISRC2_PB_0_8
R ISRC2_PB_0_9
R ISRC2_PB_0_10
R ISRC2_PB_0_11
R ISRC2_PB_0_12
R ISRC2_PB_0_13
R ISRC2_PB_0_14
R ISRC2_PB_0_15
R ISRC2_PB_0_16
R ISRC2_PB_0_17
R ISRC2_PB_0_18
R ISRC2_PB_0_19
R ISRC2_PB_0_20
R ISRC2_PB_0_21
R ISRC2_PB_0_22
R ISRC2_PB_0_23
R ISRC2_PB_0_24
R ISRC2_PB_0_25
R ISRC2_PB_0_26
R ISRC2_PB_0_27
R ISRC2_PB_0_28
Description
No ISRC2 packets received since the last HDMI packet detection reset.
ISRC2 packets have been received. This bit resets to zero after an HDMI packet detection reset or
upon writing to ISRC2_PACKET_ID.
Rev. A | Page 90 of 204
Hardware User Guide
1
Packet Byte No.
Packet type value
HB1
HB2
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27