Hdmi Receiver; +5 V Cable Detect - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237

HDMI RECEIVER

HPA_A/INT2
HPA_B
RXA_5V
RXB_5V
CEC
DDCA_SDA/DDCA_SC L
DDCB_SDA/DDCB_SC L
RXA_C±
RXB_C±
RXA_0±
EQUALIZER
RXA_1±
RXA_2±
RXB_0±
EQUALIZER
RXB_1±
RXB_2±
ADV7619 feature HDMI 1.4a compliant HDMI Receiver capable to support HDMI stream with bit rate up to 3 Gbs. HDMI stream with
bit rate below 2.25 Gbs is receiver and can be processes by CP core, where HDMI stream with bit rates above 2.25 Gbs and below 3 Gbs is
directly output to OUTPUT DATA FORMATTER. These two video paths: 2.25 Gbs and 3 Gbs are shown in Figure 4.

+5 V CABLE DETECT

The HDMI receiver in the ADV7619 can monitor the level on the +5 V power signal pin of each connected HDMI port. The results of
this detection can be read back from the following I
HDMI mode.
CABLE_DET_A_RAW, IO, Address 0x6F[0] (Read Only)
Raw status of Port A +5 V cable detection signal.
Function
CABLE_DET_A_RAW
0 (default)
1
CABLE_DET_B_RAW, IO, Address 0x6A[7] (Read Only)
Raw status of Port B +5 V cable detection signal.
Function
CABLE_DET_B_RAW
0 (default)
1
The ADV7619 provides a digital glitch filter on the +5 V power signals from the HDMI port. The output of this filter is used to reset the
HDMI block (refer to the HDMI Section Reset Strategy section).
The +5 V power signal must be constantly high for the duration of the timer (controlled by FILT_5V_DET_TIMER[6:0]), otherwise the
output of the filter is low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.
FILT_5V_DET_DIS, Addr 68 (HDMI), Address 0x56[7]
This control is used to disable the digital glitch filter on the HDMI 5 V detect signals. The filtered signals are used as interrupt flags and
used to reset the HDMI section. The filter works from an internal ring oscillator clock and, therefore, is available in power-down mode.
The clock frequency of the ring oscillator is 42 MHz ± 10%.
5V DETECT
AND HPA
CONTROLLER
CEC
CONTROLLER
EDID/
REPEATER
CONTROLLER
HDCP
PLL
EEPROM
PLL
HDCP
BLOCK
SAMPLER
SAMPLER
Figure 4. Functional Block Diagram of HDMI Core
2
C registers. These readbacks are valid even when the part is not configured for
Description
No cable detected on Port A
Cable detected on Port A (high level on RXA_5V)
Description
No cable detected on Port B
Cable detected on Port B (high level on RXB_5V)
DATA
HS
DEEP COLOR
VS
CONVERSION
DE
DATA
HS
4:2:2 TO 4:4:4
VS
CONVERSION
DE
FILTER
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
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Hardware User Guide
TO INTERRUPT
CONTROLLER
VIDEO OUTPUT
FORMATTER
(3Gbs VIDEO PATH)
TO DATA
PREPROCESSOR
(2.25Gbs VIDEO PATH)
AP0
AP1/I2S_TDM
AP2
AP3
AP4
AP5
SCLK/INT2
AUDIO MCLK/INT2
PROCESSOR