Analog Devices Advantiv ADV7619 Hardware User's Manual page 181

Hardware User Guide
CABLE_DET_B_ST , IO, Address 0x6B[7] (Read Only)
Latched status of Port B +5 V cable detection interrupt signal. Once set, this bit remains high until the interrupt has been cleared via
CABLE_DET_B_CLR. This bit is only valid if enabled via corresponding the INT1 or INT2 interrupt mask bit.
Function
CABLE_DET_B_ST Description
0 (default) CABLE_DET_B_RAW has not changed. Interrupt has not been generated from this register.
1 CABLE_DET_B_RAW has changed. Interrupt has been generated from this register.
TMDSPLL_LCK_A_ST , IO, Address 0x6B[6] (Read Only)
Latched status of Port A TMDS PLL lock interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
TMDSPLL_LCK_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
TMDSPLL_LCK_A_ST Description
0 (default) TMDSPLL_LCK_A_RAW has not changed. An interrupt has not been generated.
1 TMDSPLL_LCK_A_RAW has changed. An interrupt has been generated.
TMDSPLL_LCK_B_ST , IO, Address 0x6B[5] (Read Only)
Latched status of Port B TMDS PLL lock interrupt signal. Once set this bit will remain high until the interrupt has been cleared via
TMDSPLL_LCK_B_CLR. This bit is only valid if enabled via corresponding the INT1 or INT2 interrupt mask bit
Function
TMDS_CLK_B_ST Description
0 (default) TMDS_CLK_B_RAW has not changed. An interrupt has not been generated.
1 TMDS_CLK_B_RAW has changed. An interrupt has been generated.
TMDS_CLK_A_ST , IO, Address 0x6B[4] (Read Only)
Latched status of Port A TMDS clock detection interrupt signal. Once set, this bit remains high until the interrupt is cleared via
TMDS_CLK_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
TMDS_CLK_A_ST Description
0 (default) TMDS_CLK_A_RAW has not changed. An interrupt has not been generated.
1 TMDS_CLK_A_RAW has changed. An interrupt has been generated.
TMDS_CLK_B_ST , IO, Address 0x6B[3] (Read Only)
Latched status of Port B TMDS clock detection interrupt signal .Once set, this bit will remain high until the interrupt has been cleared
via TMDS_CLK_B_CLR. This bit is only valid if enabled via corresponding the INT1 or INT2 interrupt mask bit
Function
TMDS_CLK_B_ST Description
0  TMDS_CLK_B_RAW has not changed. An interrupt has not been generated.
1 TMDS_CLK_B_RAW has changed. An interrupt has been generated.
VIDEO_3D_ST , IO, Address 0x6B[2] (Read Only)
Latched status for the video 3D interrupt. Once set, this bit will remain high until the interrupt is cleared via VIDEO_3D_CLR. This bit is
only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
VIDEO_3D_ST Description
0 (default) VIDEO_3D_RAW has not changed. An interrupt has not been generated.
1 VIDEO_3D_RAW has changed. An interrupt has been generated.
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