Structure Of Internal E-Edid For Port B - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237

STRUCTURE OF INTERNAL E-EDID FOR PORT B

This section describes the structure of the internal E-EDID accessible through the DDC bus of Port B.
The internal E-EDID is enabled for Port B by setting the EDID_B_ENABLE bit to 1. The image of the internal E-EDID that is accessed
on the DDC bus of Port B corresponds to the data image contained in the internal E-EDID RAM except for the SPA, SPA location, and
the checksum of the E-EDID block where the SPA is located.
The structure of the internal E-EDID image for Port B is shown in the following figures:
•
Figure 6—SPA located in E-EDID Block 1
•
Figure 7—SPA located in E-EDIDBlock 2
•
Figure 8—SPA located in E-EDIDBlock 3
PORT B E-EDID STRUCTURE
0x1FF BLOCK 3 CHECKSUM
BLOCK 3
0x180
0x17F BLOCK 2 CHECKSUM
BLOCK 2
0x100
0xFF BLOCK 1 CHECKSUM
BLOCK 1
0x80
0x7F BLOCK 0 CHECKSUM
BLOCK 0
0x00
0x1FE
0x17E
0x100
0xFF
0xFE
SPA_LOCATION[8:0]+2
0x80
0x7E
0x00
Figure 6. Port B E-EDID Structure and Mapping for SPA Located in E-EDID Block 1
Rev. A | Page 36 of 204
0x1FF
PORT_B_CHECKSUM[7:0]
0xFE
SPA_PORT_B[15:0]
SPA_LOCATION[8:0]–1
0x7F
Hardware User Guide
INTERNAL EDID RAM
REPEATER MAP, REG 0x70, REG 0x71
INTERNAL EDID RAM
REPEATER MAP, REG 0x70, REG 0x71
INTERNAL EDID RAM