Analog Devices Advantiv ADV7619 Hardware User's Manual page 21

Hardware User Guide
INV_F_POL, IO, Address 0x06[3]
A control to select the polarity of the DE signal.
Function
INV_F_POL
0 (default)
1
Digital Synthesizer Controls
The ADV7619 features two digital encoder synthesizers that generate the following clocks:
•
Video DPLL: this clock synthesizer generates the pixel clock. It undoes the effect of deep color and pixel repetition that are inherent
to HDMI streams. The output of the LLC pin is either this pixel clock or a divided down version, depending on the datapath
configuration. It takes less than one video frame for this synthesizer to lock.
•
Audio DPLL: this clock synthesizer generates the audio clock. As per HDMI specification, the incomming HDMI clock is divided
down by CTS and then multiplied up by N. This audio clock is used as the main clock in the audio stream section. The output of
MCLK represents this clock. It takes less than 5 ms after a valid ACR packet for this synthesizer to lock.
Crystal Frequency Selection
The ADV7619 supports 27.0, 28.63636, 24.576 and 24.0 MHz frequency crystals. Following control allows selecting crystal frequency.
XTAL_FREQ_SEL[1:0], IO, Address 0x04[2:1]
A control to set the XTAL frequency used.
Function
XTAL_FREQ_SEL[1:0]
00
01 (default)
10
11
Description
Negative FIELD/DE polarity
Positive FIELD/DE polarity
Description
27 MHz
28.63636 MHz
24.576 MHz
24.0 MHz
Rev. A | Page 21 of 204
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