Hdmi Section Reset Strategy; Hdmi Packet Detection Flag Reset - Analog Devices Advantiv ADV7619 Hardware User's Manual

Hardware User Guide
Table 37. HDMI InfoFrame Checksum Error Flags in IO Map
Bit Name
AVI_INF_CKS_ERR_RAW
AUD_INF_CKS_ERR_RAW
SPD_INF_CKS_ERR_RAW
MS_INF_CKS_ERR_RAW
VS_INF_CKS_ERR_RAW
Table 38. AKSV Update Flags and RI expired flag in IO Map Register 0x88
Bit Name
AKSV_UPDATE_A_RAW
AKSV_UPDATE_B_RAW
RI_EXPIRED_A_RAW
RI_EXPIRED_B_RAW
Table 39. HDMI Flags in HDMI Map
Bit Name
AUDIO_PLL_LOCKED
AUDIO_SAMPLE_PCKT_DET
DSD_PACKET_DET
DST_AUDIO_PCKT_DET
HBR_AUDIO_PCKT_DET
DCFIFO_LOCKED

HDMI SECTION RESET STRATEGY

The reset strategy implemented for the HDMI section is as follows:
•
Global chip reset
A global chip reset is triggered by asserting the reset pin to a low level. The HDMI section, excluding the EDID/repeater controller, is
reset when a global reset is triggered.
•
Loss of TMDS clock or 5 V signal reset
A loss of TMDS clock or 5 V signal on the HDMI port selected via HDMI_PORT_SELECT[2:0] resets the entire HDMI section
except for the EDID/repeater controller and the audio section.
The loss of a 5 V signal condition is discarded if DIS_CABLE_DET_RST is set high.
•
DVI mode reset
The packet processing block, including InfoFrame memory is held in reset when the HDMI section processes a DVI stream.
•
EDID/repeater controller reset
The EDID/repeater controller is reset when the DVDD supplies go low or when HDCP_REPT_EDID_RESET is set high.

HDMI PACKET DETECTION FLAG RESET

A packet detection flag reset is triggered when any of the following events occur:
•
The ADV7619 is powered up.
•
The ADV7619 is reset.
•
A TMDS clock is detected, after a period of no clock activity, on the selected HDMI port.
•
The selected HDMI port is changed.
•
The signal from the 5 V input pin of the HDMI port selected through HDMI_PORT_SELECT transitions to a high. This condition is
discarded if DIS_CABLE_DET_RST is set high.
IO Map Location Description
0x88[4] Description available in the InfoFrame Checksum Error Flags section
0x88[5] Description available in the InfoFrame Checksum Error Flags section
0x88[6] Description available in the InfoFrame Checksum Error Flags section
0x88[7] Description available in the InfoFrame Checksum Error Flags section
0x8D[0] Description available in the InfoFrame Checksum Error Flags section
Bit Position Description
0 When set to 1 it indicates that transmitter has written its AKSV into HDCP
registers for Port A. Once set, this bit remains high until the interrupt is cleared
via AKSV_UPDATE_A_CLR (IO Map 0x8A[0]).
1 When set to 1 it indicates that transmitter has written its AKSV into HDCP
registers for Port B. Once set, this bit remains high until the interrupt is cleared
via AKSV_UPDATE_B_CLR (IO Map 0x8A[1]).
2
Status of Port A Ri expired interrupt signal. When set to 1, it indicates that HDCP
cipher Ri value for Port A is expired. Once set, this bit remains high until it is
cleared via RI_EXPIRED_A_CLR (HDMI Map, 0x8A[2].
3
Status of Port B Ri expired interrupt signal. When set to 1, it indicates that HDCP
cipher Ri value for Port B is expired. Once set, this bit remains high until it is
cleared via RI_EXPIRED_B_CLR (0x8A[3].
HDMI Map Location Description
0x04[0] Description available in the Locking Mechanism section
0x18[0] Description available in the Audio Packet Type Flags section
0x18[1] Description available in the Audio Packet Type Flags section
0x18[2] Description available in the Audio Packet Type Flags section
0x18[3] Description available in the Audio Packet Type Flags section
0x1C[3] Description available in the Video FIFO section
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