Llc Controls; Dll On Llc Clock Path; Changes To Dll On Llc Clock Path Section - Analog Devices Advantiv ADV7619 Hardware User's Manual

Hardware User Guide

LLC CONTROLS

The ADV7619 has a number of adjustment features available for the line locked clock (LLC) output. The polarity of the LLC can be
inverted and the LLC of the output driver can be tristated. Controls also exist to skew the LLC versus the output data to achieve suitable
setup and hold times for any back end device. The LLC controls are as follows:
•
INV_LLC_POL
•
TRI_LLC
•
LLC_DLL_EN
•
LLC_DLL_MUX
•
LLC_DLL_PHASE[4:0]

DLL ON LLC CLOCK PATH

A delay locked loop (DLL) block is implemented on the LLC clock path. This DLL allows the changing of the phase of the output
pixel clock on the LLC pin.
Adjusting DLL Phase in All Modes
LLC_DLL_EN, IO, Address 0x19[7]
A control to enable the DLL for the output pixel clock.
Function
LLC_DLL_EN
1
0 (default)
LLC_DLL_MUX, IO, Address 0x33[6]
A control to apply the pixel clock DLL to the pixel clock output on the LLC pin.
Function
LLC_DLL_MUX
0 (default)
1
LLC_DLL_PHASE[4:0], IO, Address 0x19[4:0]
A control to adjust LLC DLL phase in increments of 1/32 of a clock period.
Function
LLC_DLL_PHASE[4:0]
00000 (default)
xxxxx
LLC_DLL_DOUBLE, IO, 0x19[6]: Doubles LLC frequency.
Function
LLC_DLL_DOUBLE[6]
0 (default)
1
DLL Settings for 656, 8-/10-/12-Bit Modes
Following settings must be done in order to enable 8-/10-/12-bit 656 output:
IO Map 0x19[7] = 1 ; Enable LLC DLL
IO Map 0x33[6] = 1 ; Muxes the DLL output on LLC output
IO Map 0x19[6] = 1 ; Double the clock
Description
Enables LLC DLL
Disables LLC DLL
Description
Bypasses the DLL
Muxes the DLL output on LLC output
Description
Default
Sets one of 32 phases of DLL to vary LLC CLK
Description
Normal LLC Frequency
Double LLC Frequency
Rev. A | Page 29 of 204
UG-237