Analog Devices Advantiv ADV7619 Hardware User's Manual page 59

Hardware User Guide
ACR PACKET
DATA
TMDS CLOCK
PACKET PROCESSOR
(DISPATCH BLOCK)
DATA FROM HDCP
ENGINE/MASK
Audio DPLL
The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs.
The audio master clock is used to clock the audio processing section.
Locking Mechanism
When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL
locks within two cycles of the audio master clock after the following two conditions are met:
•
TMDS PLL is locked (refer to TMDS_PLL_LOCKED )
•
ADV7619 has received an ACR packet with N and CTS parameters within a valid range
The audio DPLL lock status can be monitored via AUDIO_PLL_LOCKED .
AUDIO_PLL_LOCKED , Addr 68 (HDMI), Address 0x04[0] (Read Only)
A readback to indicate the Audio DPLL lock status.
Function
AUDIO_PLL_LOCKED
0 (default)
1
ACR Parameters Loading Method
The N and CTS parameters from the ACR packets are used to regenerate the audio clock and are reloaded into the DPLL anytime they
change. The self-clearing bit FORCE_N_UPDATE provides a means to reset the audio DPLL by forcing a reload of the N and CTS
parameters from the ACR packet into the audio DPLL.
FORCE_N_UPDATE , Addr 68 (HDMI), Address 0x5A[0] (Self-Clearing)
A control to force an N and CTS value update to the audio DPLL. The audio DPLL regenerates the audio clock.
Function
FORCE_N_UPDATE Description
0 (default) No effect
1 Forces an update on the N and CTS values for audio clock regeneration
Audio DPLL Coast Feature
The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio master clock when selectable events occur.
The coast feature allows the audio DPLL to provide an audio master clock when the audio processor mutes the audio following a mute
condition (refer to the Audio Muting section). The events that cause the audio DPLL to coast are selected via the coasts masks listed in
Table 8.
TMDS CLOCK
N
AUDIO DPLL
CTS
AUDIO
AUDIO DATA
FIFO
TO DPP
VIDEO DATA
BLOCK
Figure 16. Audio Processor Block Diagram
Description
The audio DPLL is not locked.
The audio DPLL is locked.
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MCLK
128fs
DELAY RAMPED
LINE MUTE/UNMUTE
CHANNEL STATUS
BITS COLLECTION
UG-237
AP0
AP1
AUDIO
AP2
RECONSTRUCTION,
AP3
SERIALIZATION AND
MUXING
AP4
AP5
SCLK