Audio Fifo - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237
Table 8. Selectable Coast Conditions
HDMI Map
Bit Name Address
AC_MSK_VCLK_CHNG 0x13[6]
AC_MSK_VPLL_UNLOCK 0x13[5]
AC_MSK_NEW_CTS 0x13[3]
AC_MSK_NEW_N 0x13[2]
AC_MSK_CHNG_PORT
AC_MSK_VCLK_DET 0x13[0]

AUDIO FIFO

The audio FIFO can store up to 128 audio stereo data from the audio sample, DSD or HBR packets. Stereo audio data are added into the
FIFO from the audio packet received. Stereo audio data are retrieved from the FIFO at a rate corresponding to 128 times the audio
sampling frequency, f .
s
The status of the audio FIFO can be monitored through the status flags FIFO_UNDERFLO_RAW, FIFO_OVERFLO_RAW,
FIFO_NEAR_OVFL_RAW , and FIFO_NEAR_UFLO_RAW.
FIFO_UNDERFLO_RAW , IO, Address 0x7E[6] (Read Only)
Status of audio FIFO underflow interrupt signal. When set to 1, it indicates the audio FIFO read pointer has reached the write pointer
causing the audio FIFO to underflow. Once set, this bit will remain high until it is cleared via AUDIO_FIFO_UNDERFLO_CLR.
Function
FIFO_UNDERFLO_RAW
0 (default)
1
FIFO_OVERFLO_RAW, IO, Address 0x7E[5] (Read Only)
Status of audio FIFO overflow interrupt signal. When set to 1, it indicates audio FIFO write pointer has reached the read pointer causing
the audio FIFO to overflow. Once set, this bit will remain high until it is cleared via AUDIO_FIFO_OVERFLO_CLR.
Description
When set to 1, audio DPLL coasts if TMDS clock has any
irregular/missing pulses
When set to 1, audio DPLL coasts if TMDS PLL unlocks
When set to 1, audio DPLL coasts if CTS changes by more
than the threshold set in CTS_CHANGE_THRESHOLD[5:0]
When set to 1, audio DPLL coasts if N changes
0x13[1] When set to 1, audio DPLL coasts if active port is changed
When set to 1, audio DPLL coasts if no TMDS clock is detected
on the active port
ADDRESS ORDER
EMPTY
EMPTY
STEREO DATA N – 1
STEREO DATA N – 2
STEREO DATA 1
STEREO DATA 0
EMPTY
EMPTY
Description
Audio FIFO has not underflowed.
Audio FIFO has underflowed.
ADDRESS 63
...
...
...
ADDRESS N + 2
ADDRESS N + 1
ADDRESS N
...
...
...
ADDRESS 3
ADDRESS 2
ADDRESS 1
ADDRESS 0
Figure 17. Audio FIFO
Rev. A | Page 60 of 204
Hardware User Guide
Corresponding Status
Registers(s)
VCLK_CHNG_RAW
TMDS_PLL_LOCKED
CTS_PASS_THRSH_RAW
CHANGE_N_RAW
HDMI_PORT_SELECT[2:0]
TMDS_CLK_A_RAW
TMDS_CLK_B_RAW
WRITE POINTER
READ POINTER