Analog Devices Advantiv ADV7619 Hardware User's Manual page 131

Hardware User Guide
CH1_STDI_DVALID , Addr 44 (CP), Address 0xB1[7] (Read Only)
This bit is set when the measurements performed by Sync Channel 1 STDI are completed. High level signals validity for CH1_BL,
CH1_LCF, CH1_LCVS, CH1_FCL, and CH1_STDI_INTLCD parameters. To prevent false readouts, especially during signal acquisition,
CH1_SDTI_DVALID only goes high after four fields with same length are recorded. As a result, STDI measurements can take up to five
fields to finish.
Function
CH1_STDI_DVALID
0 (default)
1
CP_STDI_INTERLACED , IO, Address 0x12[4] (Read Only)
A readback to indicate the interlaced status of the currently selected STDI block applied to the CP core.
Function
CP_STDI_INTERLACED
0 (default)
1
CP_INTERLACED , IO, Address 0x12[3] (Read Only)
A readback to indicate the interlaced status of the CP core based on configuration of video standard and INTERLACED bit in the CP map.
Function
CP_INTERLACED
0 (default)
1
CP_PROG_PARM_FOR_INT , IO, Address 0x12[2] (Read Only)
A readback to indicate if the CP core is processing for progressive standard while the vdeo standard and the INTERLACED bit in the CP
map are configured for an interlaced standard.
Function
CP_PROG_PARM_FOR_INT
0 (default)
1
CP_FORCE_INTERLACED , IO, Address 0x12[1] (Read Only)
A readback to indicate forced-interlaced status of the CP core based on configuration of video standard and INTERLACED bit in the CP map.
Function
CP_FORCE_INTERLACED
0 (default)
1
Description
Sync Channel 1 STDI measurements are not valid.
Sync Channel 1 STDI measurements are valid.
Description
Selected STDI has detected a progressive input.
Selected STDI has detected a interlaced input.
Description
CP core is processing the input as a progressive input.
CP core is processing the input as a interlaced input.
Description
CP core processing for a progressive standard while video standard and the INTERLACED bits are
configured for an interlaced standard
CP core processing for a progressive standard while video standard and the INTERLACED bits+ are
configured for a progressive standard
Description
Input is detected as interlaced and the CP is programmed in an interlaced mode via VID_STD[5:0].
Input is detected as progressive and the CP is programmed in an interlaced mode.
Rev. A | Page 131 of 204
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