Interface To Dpp Section - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237
Register Name Address Location
SHA_D[31:0] 0x2C[7:0]: SHA_D[7:0]
0x2D[7:0]: SHA_D[15:8]
0x2E[7:0]: SHA_D[23:16]
0x2F[7:0]: SHA_D[31:24]
SHA_E[31:0] 0x30[7:0]: SHA_E[7:0]
0x31[7:0]: SHA_E[15:8]
0x32[7:0]: SHA_E[23:16]
0x33[7:0]: SHA_E[31:24]
1
All registers specified in Table 29 are located in the repeater map.
2
Refer to HDCP protection system Standards.

INTERFACE TO DPP SECTION

The video databelow 2.25Gbps from the HDMI section is sent to the CP section via the DPP block. The video data output by the HDMI
section is always in a 4:4:4 format with 36 bits per pixel. This is irrespective of the encoding format of the video data encapsulated in the
HDMI/DVI stream input to the HDMI receiver section (that is, 4:2:2 or 4:4:4).

If the HDMI section receives a stream with video encoded in a 4:4:4 format, it passes the video data to the DPP section.

If the HDMI section receives a stream with video encoded in a 4:2:2 format (refer to Figure 29), the HDMI section upconverts the
video data into a 4:4:4 format, according to the UP_CONVERSION_MODE bit, and passes the upconverted video data to the DPP
section (refer to Figure 30).

If the HDMI receiver receives video data with fewer than 12 bits used per channel, the valid bits are left-shifted on each component
channel with zeroes padding the bit below the LSB, before being sent to the DPP section.

If the HDMI receiver receives video data above 2.25 GBps, data must be send directly to the video ouput formatter, bypassing the
DPP and CP core, where it is output using two video buses running at half pixel clock frequency
TMDS
CHANNEL
0
1
2
COMPONENT
CHANNEL
Y
Cb
Cr
1
Y /Cb Y
0 0 1
Y BITS[3:0] Y BITS[3:0]
BITS[3:0]
0 1
BITS[7:4] Cb BITS[3:0] Cr BITS[3:0]
0 0
BITS[7:0]
Y BITS[11:4] Y BITS[11:4]
0 1
BITS[7:0]
Cb BITS[11:4] Cr BITS[11:4]
0 0
Figure 29. YC C 4:2:2 Video Data Encapsulated in HDMI Stream
b r
Y /Cb /Cr Y /CR
0 0 0 1
BITS[12:0] Y
0
BITS[12:0]
Cb
0
BITS[12:0]
Cr
0
Figure 30. Video Stream Output by HDMI Core for YC
Function
H3 part of SHA-1 hash value V' . Register also called (V' . H3)
H4 part of SHA-1 hash value V' . Register also called (V' . H4)
/Cr Y /Cb Y /Cr
0 2 2 3
Y BITS[3:0] Y BITS[3:0]
2 3
Cb BITS[3:0] Cr BITS[3:0]
2 2
Y BITS[11:4] Y BITS[11:4]
2 3
Cb BITS[11:4] Cr BITS[11:4]
2 2
/CR Y /Cb /Cr Y /Cb
0 0 2 2 2 3
Y Y
1 2
Cb Cb Cb
0 2
Cr Cr Cr
0 2
C 4:2:2 Input and UP_CONVERSION = 0
b r
Rev. A | Page 100 of 204
Hardware User Guide
...
Y /Cb
2 4 2
...
Y BITS[3:0]
4
...
Cb BITS[3:0]
4
...
Y BITS[11:4]
4
...
Cb BITS[11:4]
4
...
/Cr Y /Cb /Cr
2 2 4 4 4
...
Y Y
3 4
...
Cb
2 4
...
Cr
2 4
2
2