Added Endnote 1 To Table 76; Pixel Output Formats - Analog Devices Advantiv ADV7619 Hardware User's Manual

UG-237
APPENDIX C

PIXEL OUTPUT FORMATS

Table 76. SDR 4:2:2 Output Modes
OP_FORMAT_SEL[7:0] 0x0
8-Bit SDR
ITU-R BT.656
Pixel Output Mode 0
P47 High-Z
P46 High-Z
P45 High-Z
P44 High-Z
P43 High-Z
P42 High-Z
P41 High-Z
P40 High-Z
P39 High-Z
P38 High-Z
P37 High-Z
P36 High-Z
P35 High-Z
P34 High-Z
P33 High-Z
P32 High-Z
P31 High-Z
P30 High-Z
P29 High-Z
P28 High-Z
P27 High-Z
P26 High-Z
P25 High-Z
P24 High-Z
P23 Y7, Cb7, Cr7
P22 Y6, Cb6, Cr6
P21 Y5, Cb5, Cr5
P20 Y4, Cb4, Cr4
P19 Y3, Cb3, Cr3
P18 Y2, Cb2, Cr2
P17 Y1, Cb1, Cr1
P16 Y0, Cb0, Cr0
P15 High-Z
P14 High-Z
P13 High-Z
P12 High-Z
P11 High-Z
P10 High-Z
P09 High-Z
P08 High-Z
P07 High-Z
P06 High-Z
P05 High-Z
P04 High-Z
P03 High-Z
P02 High-Z
P01 High-Z
P00 High-Z
1
Refer to the DLL Settings for 656, 8-/10-/12-Bit Modes section in chapter DLL on LLC Clock Path.
0x1
10-Bit SDR
ITU-R BT.656
1 1
Mode 0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Rev. A | Page 198 of 204
SDR 4:2:2
0x2 0x6
12-Bit SDR 12-Bit SDR
ITU-R BT.656 ITU-R BT.656
1
Mode 0 Mode 1
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z Y1, Cb1, Cr1
High-Z Y0, Cb0, Cr0
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Y11, Cb11, Cr11 Y11, Cb11, Cr11
Y10, Cb10, Cr10 Y10, Cb10, Cr10
Y9, Cb9, Cr9 Y9, Cb9, Cr9
Y8, Cb8, Cr8 Y8, Cb8, Cr8
Y7, Cb7, Cr7 Y7, Cb7, Cr7
Y6, Cb6, Cr6 Y6, Cb6, Cr6
Y5, Cb5, Cr5 Y5, Cb5, Cr5
Y4, Cb4, Cr4 Y4, Cb4, Cr4
Y3, Cb3, Cr3 Y3, Cb3, Cr3
Y2, Cb2, Cr2 Y2, Cb2, Cr2
Y1, Cb1, Cr1 High-Z
Y0, Cb0, Cr0 High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
Hardware User Guide
0x0A
12-Bit SDR
ITU-R BT.656
1 1
Mode 2
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y3, Cb3, Cr3
Y2, Cb2, Cr2
Y1, Cb1, Cr1
Y0, Cb0, Cr0
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Y11, Cb11, Cr11
Y10, Cb10, Cr10
Y9, Cb9, Cr9
Y8, Cb8, Cr8
Y7, Cb7, Cr7
Y6, Cb6, Cr6
Y5, Cb5, Cr5
Y4, Cb4, Cr4
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z