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A16 REFERENCE
A16A1 REFERENCE DAUGHTER
2400 MHz
O
X8
f
ALC
ALC
4.8 GHz
HP
HP
J724
J725
300 MHz
LP
LP
J723
50 MHz
2
ALC
300 MHz
100 MHz
X3
O
NF
10
f
R
O
f
1 to 16
1 - 50 MHz
J704
EXT REF INPUT
10 MHz
(rear panel)
W37
blockpxa_ref_synth
4.8 GHz
2nd LO
X2
2nd LO
2400 MHz
SAW VCO
2.4 GHz Ref
HARMONIC
GEN
CAL OUT
EXT FE CAL INPUT
ECAL OUT
COMB
COMB
SER
GEN
LVDS
10 dB
MOD
+10 dBm
300 MHz LO_AIF
300 MHz
+13 dBm
100 MHz LO_SYNTH
SAW
+10 dBm
100 MHz REF_A
+13 dBm
100 MHz REF_B
100 MHz REF_C
10 MHz
10 MHz
10 MHz OUT_DIF
DAC
Card Cage
Connector
A14 LO SYNTHESIZER
Card Cage
Connector
FPGA
(from A8)
J1
LO
J702 +11 dBm
Serial Bus &
CONTROLLER
Sync/Swp Signals
W18 to A13J1
From Serial
J703 Note 1
Offset PLL
J718 +10 dBm
4800 MHz
W34 to A25J301
1st LO Ref
(from A16)
J4
Note 1
W31
100 MHz
LO/SYNTH
Ref
2, 3
(from A16)
or 6
J10
50 MHz -25 dBm
J701
4.8 GHz -28 dBm
W32
W3 to A9
J726
W47 to A3J17 or
W46 to A25J806
J705
-26 to -29 dBm
W33 to A13J6
J714
EXT ECAL IN
OFFSET
LOOP
J711
CONTROL
W36 to A2J300
J706
W32 to A14J10
J707
W35 to A19J101 (Opt BBA)
J716
W39 to A3J14
J717
J710
NOTES
1
Power Level is ~ +3 dBm in Dual-Loop mode and ~ -20 dBm in Single-Loop mode.
2
The Tuning Equation below shows the relationship between the YTO frequency (1st LO) and
the Tuned Frequency.
Band
Tuning Equation
0 - 3.6 GHz
YTO = Tuned Freq + 5.1225 GHz
3.6 - 8.4 GHz
YTO = Tuned Freq + 322.5 GHz
8.4 - 13.6 GHz
YTO = (Tuned Freq + 322.5 MHz) / 2
13.6 - 17.1 GHz
YTO = (Tuned Freq + 322.5 MHz) / 2
17.1 - 26.5 GHz
YTO = (Tuned Freq + 322.5 MHz) / 4
26.4 - 34 GHz
YTO = (Tuned Freq + 322.5 MHz) / 4
YTO = (Tuned Freq + 322.5 MHz) / 8
34 - 50 GHz
3
When autocoupled, spans > 10 MHz are Single-Loop spans
and < 10 MHz are Dual-Loop spans.
A20 YTO
MAIN LOOP
YTO
Pretune
DRIVER
DAC
FN
CONTROLLER
W23
MAIN LOOP
CONTROL
Dual
J25
Loop
YTO MAIN
FRACTIONAL
O
and FM COIL
N
f
DRIVERS
Note
DIVIDER
Single
3
Loop
Note 3
Single
Dual
2
Loop
Loop
33 to 55 MHz
50 MHz
IF
RF
LO
OFFSET LOOP
1.14 to
2.3 GHz
X2
O
f
16.6 or 33.3 MHz
PROGRAMMABLE
3
SERIAL
DIVIDER/COUNTER
DATA
3.5 to
9.06 GHz
LO
IF
RF
0 TO 4.2 GHz
4.8 GHz
PXA REFERENCE and
SYNTHESIZER BLOCK DIAGRAM
A13A1 Front End
To Mixer 1
3.8 TO
LO
8.73 GHz
DISTRIBUTION
J4
W20
To Mixer 2
and Mixer 3
+10 dBm
Note 2
J5
J3
W19
W21
SYNTH
to A13A2
SWITCHED
OUT
+10 dBm
FILTER
+9 dBm
J20
4.5 to 9.06 GHz
2.28 to 4.5 GHz
X2
PLL MUX OUT
to FPGA
16.6 or
33.3 MHz
SWITCHED BPF
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