Sun Microsystems SPARCcenter 2000 Service Manual page 257

The main sections of the system are interconnected by the system bus, which is
called an XDBus.
Main memory unit
Memory Memory
bank bank
BW BW BW
XBus
MXCC
SMXX
RAM
Processor module Processor module
Figure B-3
The XDBus is the main system bus. The XDBus is the backplane bus in the
main card cage and the system bus on the system board. BICs interconnect the
on-board and backplane XDBus. BICs are 18-bit bit-sliced pipeline registers.
Each XDBus is supported by four BICs.
For high-speed system operation, the XDBus is divided into two independent
halves. Either half of the XDBus can be accessed by SBus cards via the SBus
interface (SBI) and the XBus. The SBI transfers data between the SBus and the
XBus.
Functional Description
BW
I/O
XBus
MXCC
I/O unit
SMXX
RAM
SBus SBus
card card
SPARCcenter 2000 System, Logical Block Diagram
Main memory unit
Memory Memory
bank bank
I/O I/O
XBus
RAM
SBI
I/O unit
SBus SBus SBus SBus
card card card card
B
XDBus
XDBus
I/O
XBus
RAM
SBI
SBus SBus
card card
B-3