Port0:144H / Port1:344H H_Chrintstat (Host Chr Interrupt Status) - Epson S2R72V18 Technical Manual

3.3.4

Port0:144h / Port1:344h H_CHrIntStat (Host CHr Interrupt Status)

Base Address: Port0=000h, Port1=200h
Mode Ofst Adrs
Host 144h H_CHrIntStat
This indicates channel CHr interrupts.
Bit7-5 Reserved
Bit4 H_CHeIntStat
Indirectly specifies interrupt factors.
Set to "1" when the H_CHeIntStat register contains an interrupt factor and the H_CHeIntEnb
register bit corresponding to that interrupt factor is enabled.
Bit3 H_CHdIntStat
Indirectly specifies interrupt factors.
Set to "1" when the H_CHdIntStat register contains an interrupt factor and the H_CHdIntEnb
register bit corresponding to that interrupt factor is enabled.
Bit2 H_CHcIntStat
Indirectly specifies interrupt factors.
Set to "1" when the H_CHcIntStat register contains an interrupt factor and the H_CHcIntEnb
register bit corresponding to that interrupt factor is enabled.
Bit1 H_CHbIntStat
Indirectly specifies interrupt factors.
Set to "1" when the H_CHbIntStat register contains an interrupt factor and the H_CHbIntEnb
register bit corresponding to that interrupt factor is enabled.
Bit0 H_CHaIntStat
Indirectly specifies interrupt factors.
Set to "1" when the H_CHaIntStat register contains an interrupt factor and the H_CHaIntEnb
register bit corresponding to that interrupt factor is enabled.
S2R72V18 Technical Manual (Rev.1.00)
Register Name R/W
7:
6:
5:
R 4: H_CHeIntStat
R 3: H_CHdIntStat
R 2: H_CHcIntStat
R 1: H_CHbIntStat
R 0: H_CHaIntStat
Bit Symbol
0:
0:
0:
0: None
0: None
0: None
0: None
0: None
EPSON
3. Register Details
Description
1:
1:
1:
1: CHe Interrupt
1: CHd Interrupt
1: CHc Interrupt
1: CHb Interrupt
1: CHa Interrupt
Reset
00h
329