Port0:000H / Port1:200H Mainintstat (Main Interrupt Status) - Epson S2R72V18 Technical Manual

Table of Contents

Advertisement

3.1.1

Port0:000h / Port1:200h MainIntStat (Main Interrupt Status)

Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
000h
Device
MainIntStat
/ Host
Indicates the interrupt factors for the LSI.
This register includes bits that directly and indirectly specify the interrupt factors. The bit for indirectly
specifying interrupt factors can read the corresponding interrupt status registers to follow the bit for directly
specifying interrupt factors. The bit for indirectly specifying interrupt factors is read-only and is automatically
cleared by clearing the bit for directly specifying major interrupt factors. The bit for directly specifying interrupt
factors can be written to; writing "1" to this bit allows the interrupt factor to be cleared. Setting the interrupt
factor to "1" when the corresponding bit interrupt is enabled by the MainIntEnb register asserts the XINT
terminal and issues an interrupt to the CPU. Clearing all corresponding interrupt factors negates the XINT
terminal.
Bit7
USB_DeviceIntStat (Port0), N/A(Port1)
Indirectly specifies interrupt factors.
This bit is not defined for Port 1.
It is set to "1" when the USB_DeviceIntStat register includes interrupt factors and the
USB_DeviceIntEnb register bit corresponding to the interrupt factors is enabled. This bit allows
reading even in SLEEP state.
Bit6
USB_HostIntStat
Indirectly specifies interrupt factors.
It is set to "1" when the USB_HostIntStat register includes interrupt factors and the
USB_HostIntEnb register bit corresponding to the interrupt factors is enabled. This bit allows
reading even in SLEEP state.
Bit5
CPU_IntStat
Indirectly specifies interrupt factors.
It is set to "1" when the CPU_IntStat register includes interrupt factors and the CPU_IntEnb register
bit corresponding to the interrupt factors is enabled.
S2R72V18 Technical Manual (Rev.1.00)
R/W
Bit Symbol
R
7: USB_DeviceIntStat
R
6: USB_HostIntStat
R
5: CPU_IntStat
R
4: FIFO_IntStat
3:
2:
1:
R (W)
0: FinishedPM
EPSON
Description
0: None
1: USB Device Interrupts
0: None
1: USB Host Interrupts
0: None
1: CPU Interrupts
0: None
1: FIFO Interrupts
0:
1:
0:
1:
0:
1:
0: None
1:Detect FinishedPM
3. Register Details
Reset
00h
207

Advertisement

Table of Contents
loading

Table of Contents