Epson S2R72V18 Technical Manual page 274

Bit3 CS_Mode
This sets the DMA operating mode.
0: Operates with DMA access enabled when XDACK is asserted.
1: Operates with DMA access enabled when XCS and XDACK are asserted.
Bit2 CPU_Endian
This indicates the CPU bus setting.
0: Sets even addresses first and odd addresses last.
1: Sets even addresses last and odd addresses first.
This bit indicates the value written to the CPUIF_MODE register during the initialization period.
Bit1 BusMode
This indicates the CPU operating mode setting.
0: 16bit Strobe mode
1: 16bit BE mode
This bit indicates the value written to the CPUIF_MODE register during the initialization period.
Bit0 Initialized
This flag indicates that initialization is complete. It is normally read as "1."
S2R72V18 Technical Manual (Rev.1.00)
EPSON
3. Register Details
257