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3. Register Details
3.2.43
Port0:0F3h / Port1:N/A D_EP0ControlOUT (Device EP0 Control OUT)
Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
Device
0F3h
D_EP0ControlOUT
This indicates the operation settings and status for endpoint EP0 OUT transactions.
Bit7
AutoForceNAK
This sets the register ForceNAK bit to "1" once the endpoint EP0 OUT transaction ends normally.
Bit6-5
Reserved
Bit4
ToggleStat
This indicates the endpoint EP0 OUT transaction toggle sequence bit state.
Bit3
ToggleSet
This sets the endpoint EP0 OUT transaction toggle sequence bit to "1." If set at the same time as the
ToggleClr bit, the ToggleClr bit function is given precedence.
Bit2
ToggleClr
This clears the endpoint EP0 OUT transaction toggle sequence bit to "0." If set at the same time as
the ToggleSet bit, this bit function is given precedence.
Bit1
ForceNAK
Setting this bit to "1" returns a NAK response to the endpoint EP0 OUT transaction, regardless of
the FIFO free space.
The USB_DeviceIntStat register RcvEP0SETUP bit is set to "1" on completion of the setup stage.
This bit is then set to "1" and cannot be cleared to "0" while the D_SETUP_Control.ProtectEP0 bit
is "1."
If the transaction is already running when this bit is set to "1," the bit is not set until the transaction
ends. It is set to "1" once the transaction ends. The bit is set to "1" immediately if the transaction is
not underway.
308
R/W
Bit Symbol
R/W
7: AutoForceNAK
0: Do nothing
6:
0:
5:
0:
R
4: ToggleStat
Toggle sequence bit
W
3: ToggleSet
0: Do nothing
W
2: ToggleClr
0: Do nothing
R/W
1: ForceNAK
0: Do nothing
R/W
0: ForceSTALL
0: Do nothing
EPSON
Description
1: Auto Force NAK
1:
1
1: Set Toggle sequence bit
1: Clear Toggle sequence bit
1: Force NAK
1: Force STALL
S2R72V18 Technical Manual (Rev.1.00)
Reset
00h
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