Epson S2R72V18 Technical Manual page 179

1. Functions
XWRL(XWR)
*1:
*2: This must be set.
*3: Temporarily negate the chip select signal ( 1 ).
*4: Assert the chip select signal (e.g., same writing as for mode setup).
*5: Checking is recommended (register access is possible even if not checked).
*6: The mode set can be checked.
Signals other than those included in Fig. 1-76 in mode setup can be either High or Low, provided the
AC ratings are satisfied.
The CPUIF mode must always be set after a hard reset, and only while uninitialized period.
The following CPUIF descriptions primarily explain Strobe and Big-endian modes.
162
CA
CD
*1
XCS
XRD
Mode setup *2
Awaiting mode setup
ENDIAN mode BUS mode
Big endian Strobe
Big endian
Little endian Strobe
Little endian
Fig. 1-76 CPUIF mode setup
*1
*3
Mode
confirmation *4
CD[15:0]
****_*00*_****_*00*
BE ****_*01*_****_*01*
****_*10*_****_*10*
BE ****_*11*_****_*11*
" "
EPSON
S2R72V18 Technical Manual (Rev.1.00)
0B7h
*6
*3
Mode check *5
Register access
permitted