Table of Contents
Advertisement
3. Register Details
3.2.61
Port0:126h / Port1:N/A D_EP_DMA_Ctrl (Device EP DMA Control)
Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
Device
126h
D_EP_DMA_Ctrl
This indicates and sets the FIFO state during DMA transfers.
Bit7
FIFO_Running
This indicates that the endpoint FIFO connected to the DMA is operating. It is set to "1" when
DMA is started and is cleared to "0" when the FIFO becomes empty after DMA ends.
Bit6
AutoEnShort
This sets the corresponding endpoint EnShortPkt bit to "1" if the amount of data remaining in the
FIFO is less than the maximum packet size after DMA ends.
It is enabled when the endpoint connected to DMA is in the IN direction.
Bit5-0
Reserved
318
R/W
Bit Symbol
R
7: FIFO_Running
0: FIFO is not running
R/W
6: AutoEnShort
0: Do nothing
5:
0:
4:
0:
3:
0:
2:
0:
1:
0:
0:
0:
EPSON
Description
1: FIFO is running
1: Auto Enable Short Packet
1:
1:
1:
1:
1:
1:
S2R72V18 Technical Manual (Rev.1.00)
Reset
00h
Advertisement
Table of Contents
