(Area 0 End Address High, Low); (Area 1 End Address High, Low); (Area 2 End Address High, Low); (Area 3 End Address High, Low) - Epson S2R72V18 Technical Manual

3.1.87 Port0:082h-083h / Port1:282h-283h AREA0EndAdrs_H,L

(AREA 0 End Address High, Low)

3.1.88 Port0:086h-087h / Port1:286h-287h AREA1EndAdrs_H,L

(AREA 1 End Address High, Low)

3.1.89 Port0:08Ah-08Bh / Port1:28Ah-28Bh AREA2EndAdrs_H,L

(AREA 2 End Address High, Low)

3.1.90 Port0:08Eh-08Fh / Port1:28Eh-28Fh AREA3EndAdrs_H,L

(AREA 3 End Address High, Low)

3.1.91 Port0:092h-093h / Port1:292h-293h AREA4EndAdrs_H,L

(AREA 4 End Address High, Low)

3.1.92 Port0:096h-097h / Port1:296h-297h AREA5EndAdrs_H,L

(AREA 5 End Address High,Low)

Base Address: Port0=000h, Port1=200h
Mode Ofst Adrs
Device 082h-083h AREA0EndAdrs_H,L
/ Host 086h-087h AREA1EndAdrs_H,L
08Ah-08Bh AREA2EndAdrs_H,L
08Eh-08Fh AREA3EndAdrs_H,L
092h-093h AREA4EndAdrs_H,L
096h-097h AREA5EndAdrs_H,L
These set the FIFO areas used by AREAx{x=0-5}.
Bit15-13 Reserved
Bit12 -2 EndAdrs[12:2]
This sets the subsequent byte of the final address of the FIFO assigned to the FIFO area
AREAx{x=0-5}.
The address is specified in 4-byte units, since it is set with 2 to 12 higher bits.
The area assigned to the FIFO area AREAx{x=0-5} extends up to the first byte of the address set by
AREAx{x=0-5}EndAdrs.
The AREAnFIFO_Clr register ClrAREAx{x=0-5} bit must always be set to "1" and the FIFO area
AREAx{x=0-5} FIFO cleared after setting AREAx{x=0-5}StartAdrs and AREAx{x=0-5}EndAdrs.
S2R72V18 Technical Manual (Rev.1.00)
Register Name R/W
15:
14:
13:
12: EndAdrs[12]
11: EndAdrs[11]
10: EndAdrs[10]
9: EndAdrs[9]
8: EndAdrs[8]
R/W
7: EndAdrs[7]
6: EndAdrs[6]
5: EndAdrs[5]
4: EndAdrs[4]
3: EndAdrs[3]
2: EndAdrs[2]
1:
0:
Bit Symbol
0:
0:
0:
AREAx{x=0-5} End Address
EPSON
3. Register Details
Description
1:
1:
1:
Reset
0000h
261