Interrupt In Transaction - Epson S2R72V18 Technical Manual

1.4.3.6

Interrupt IN Transaction

The transfer type (H_CHx{x=b-e}Config_1.TranType) is set to "Interrupt" and the transaction type
(H_CHx{x=b-e}Config_1.TID) is set to "IN" for the CHx{x=b-e} basic setting register. The
token-issuing interval (H_CHx{x=b-e}Interval_H,L), other basic settings, and transfer execution
(H_CHx{x=b-e}Config_0.TranGo) are set appropriately, subjecting the channel to hardware-based
USB transfer scheduling. The token-issuing interval (H_CHx{x=b-e}Interval_H,L), FIFO free
space, and remaining frame time are determined when the corresponding channel is selected by
scheduling, and an interrupt IN transaction is executed.
The data length expected of the data packets to be received is the smaller of
H_CHx{x=b-e}MaxPacketSize_H,L and H_CHx{x=b-e}TotalSize_HH,HL,LH,LL.
If all data is received normally during the interrupt IN transaction, an ACK response is returned,
and the transaction ends. An ACK status notification (H_CHx{x=b-e}IntStat.TranACK bit) is also
issued to the firmware. The FIFO is then updated, reserving space by treating the data as already
received.
If the data length received is shorter than the data length expected for the interrupt IN transaction,
H_CHx{x=b-e}Config_0.TranGo is automatically cleared, ending the transfer and returning an
ACK response. The condition code (H_CHx{x=b-e}ConditionCode) is set to "DataUnderrun." A
ChangeCondition status notification (H_CHx{x=b-e}IntStat.ChangeCondition bit) is then issued to
the firmware. The FIFO is updated and the area is reserved by treating the data as already received.
If a NAK is received for the interrupt IN transaction, no status notification is issued, and the FIFO is
not updated. The next transaction is performed in the next cycle.
If STALL is received for the interrupt IN transaction, H_CHx{x=b-e}Config_0.TranGo is
automatically cleared, ending the transfer, and the condition code (H_CHx{x=b-e}ConditionCode)
is set to "STALL." A ChangeCondition status notification
(H_CHx{x=b-e}IntStat.ChangeCondition bit) is then issued to the firmware. The FIFO is not
updated.
If the data length received is longer than the data length expected for the bulk IN transaction,
H_CHx{x=b-e}Config_0.TranGo is automatically cleared, ending the transfer. No response is
returned. The condition code (H_CHx{x=b-e}ConditionCode) is set to "DataOverrun." A
ChangeCondition status notification (H_CHx{x=b-e}IntStat.ChangeCondition bit) is then issued to
the firmware. The FIFO is not updated.
If a toggle mismatch occurs for the interrupt IN transaction, an ACK response is returned. The
condition code (H_CHx{x=b-e}ConditionCode) is set to "RetryError," and a TranErr status
notification (H_CHx{x=b-e}IntStat.TranErr bit) is issued to the firmware. The FIFO is not updated.
If a timeout error, CRC error, bit stuffing error, or PID error (including unforeseen PID) occurs for
the interrupt IN transaction, no response is returned. The condition code
(H_CHx{x=b-e}ConditionCode) is set to "RetryError," and a TranErr status notification
(H_CHx{x=b-e}IntStat.TranErr bit) is issued to the firmware. The FIFO is not updated.
S2R72V18 Technical Manual (Rev.1.00)
EPSON
1. Functions
63