3. Register Details
3.2.12
Port0:0C0h / Port1:N/A D_SIE_IntEnb (Device SIE Interrupt Enable)
Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
Device
0C0h
D_SIE_IntEnb
This permits or prohibits assertion of the MainIntStat register D_SIE_IntStat bit using the D_SIE_IntStat register
interrupt factors.
The EnNonJ bit is enabled even in SLEEP state.
282
R/W
Bit Symbol
7:
R/W
6: EnNonJ
R/W
5: EnRcvSOF
R/W
4: EnDetectRESET
R/W
3: EnDetectSUSPEND
R/W
2: EnChirpCmp
R/W
1: EnRestoreCmp
R/W
0: EnSetAddressCmp
EPSON
Description
0:
1:
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
S2R72V18 Technical Manual (Rev.1.00)
Reset
00h