Epson S2R72V18 Technical Manual page 257

3. Register Details
3.1.31 Port0:032h / Port1:232h RAM_RdControl (RAM Read Control)
Base Address: Port0=000h, Port1=200h
Mode Ofst Adrs Register Name
Device 032h RAM_RdControl
/ Host
Bit7 RAM_GoRdCBW_CSW
This bit starts the RAM_Rd function to read out data received in the CBW area when the device is
operating or CSW area during host operation.
Writing "1" to this bit when the device is operating starts the RAM_Rd function and reads data
from the CBW area. When the values of registers RAM_Rd_00 to RAM_Rd_1E become valid, the
CPU_IntStat.RAM_RdCmp bit is set to "1," and the bit is automatically cleared.
Writing "1" to this bit during host operation starts the RAM_Rd function and reads data from the
CSW area. When the values of registers RAM_Rd_00 to RAM_Rd_0C become valid, the
CPU_IntStat.RAM_RdCmp bit is set to "1," and the bit is automatically cleared.
In either case, the RAM_RdAdrs_H,L or RAM_RdCount registers need not be set.
The function for this bit takes priority if it is set concurrently with the RAM_GoRd bit.
Bit6 RAM_GoRd
This bit starts the RAM_Rd function.
Setting the RAM_RdCount register and writing "1" to this bit after setting the initial address for
RAM_Rd in the RAM_RdAdrs_H,L registers starts the RAM_Rd function. Once the specified
count quantity of data has been read from the initial address specified and the RAM_Rd_xx{xx=00
to 1F} register value is enabled, the CPU_IntStat.RAM_RdCmp bit is set to "1," and the bit is
automatically cleared.
The function for the RAM_GoRdCBW_CSW bit takes priority if set concurrently with the
RAM_GoRdCBW_CSW bit.
Bit5-0 Reserved
240
R/W Bit Symbol
R/W 7: RAM_GoRdCBW_CSW
R/W 6: RAM_GoRd
5:
4:
3:
2:
1:
0:
EPSON
Description
0: Do nothing 1: RAM Read CBW_CSW start
0: Do nothing 1: RAM Read start
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
0: 1:
S2R72V18 Technical Manual (Rev.1.00)
Reset
00h