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3. Register Details
3.1.9
Port0:00Ah / Port1:20Ah USB_HostIntEnb (Host Interrupt Enable)
Base Address: Port0=000h, Port1=200h
Mode
Ofst Adrs
Register Name
Device
00Ah
USB_HostIntEnb
/ Host
Permits or prohibits MainIntStat register USB_HostIntStat bit assertion by USB_HostIntStat register interrupt
factors.
The EnVBUS_Err bit and EnLineStateChanged bit are enabled even in SLEEP state.
218
R/W
Bit Symbol
R/W
7: EnVBUS_Err
R/W
6: EnLineStateChanged
R/W
5: EnH_SIE_IntStat1
R/W
4: EnH_SIE_IntStat0
R/W
3: EnH_FrameIntStat
R/W
2:
R/W
1: EnH_CH0IntStat
R/W
0: EnH_CHrIntStat
EPSON
Description
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0: Disable
1: Enable
0:
1:
0: Disable
1: Enable
0: Disable
1: Enable
S2R72V18 Technical Manual (Rev.1.00)
Reset
00h
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