Req Assert Count Option (Write) - Epson S2R72V18 Technical Manual

1. Functions
The operational timing is the same as for Count mode, except that no restrictions apply due
to DMA_Count_HH,HL,LH,LL.
1.7.3.2.7

REQ Assert Count Option (Write)

[Operation start]
Set the assert count using the DMA_Config.ReqAssertCount[1:0] bit, then set the
DMA_Control.DMA_Go bit to "1." XDREQ is asserted and DMA transfer enabled if free
space for writing in the internal FIFO is at least equal to the assert count number. Thus, the
transfer of the assert count quantity set is guaranteed if XDREQ is asserted temporarily.
However, XDREQ is asserted, even if the free space is less than the assert count, if the free
space is at least equal to the remaining count when set to count mode. In this case, the
guaranteed transfer quantity will be the remaining count.
XDREQ is temporarily negated for each transfer quantity set by the ReqAssertCount[1:0] bit
in this mode.
"1" can be read in the DMA_Control.DMA_Running bit until the operation halts.
[Operation stop]
For detailed information on operation stop conditions, refer to "1.7.3.2.3 Count Mode
(Write)" and "1.7.3.2.5 Free-run Mode (Write)."
Ex: Transfer start: REQ assert count (8-beat: 16-byte)
XDREQ
XDACK
DATA
XCS
XWRL,H
(1) Start DMA circuit operations by writing "1" to the DMA_Control.DMA_Go bit.
XDREQ is not asserted since the DMA_Ready value is less than the continuous transfer
quantity.
(2) Transferring data from the USB creates valid free space in the FIFO (DMA_Ready)
exceeding the continuous transfer quantity. XDREQ is asserted on receipt of DMA_Ready.
(3) XDREQ is negated when the continuous transfer quantity (REQ assert count) is complete.
(4) Free space for the next continuous transfer (DMA_Ready) exists once the first continuous
transfer is complete. DREQ is asserted on receipt of DMA_Ready.
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Fig. 1-84 REQ assert count option write timing
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EPSON
S2R72V18 Technical Manual (Rev.1.00)
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