Count Mode (Read) - Epson S2R72V18 Technical Manual

1. Functions
1.7.3.2.4

Count Mode (Read)

[Operation start]
Set the DMA_Count_HH,HL,LH,LL registers to the count value, then set the
DMA_Control.DMA_Go bit to "1." XDREQ is asserted and reading from externally is
enabled if the internal FIFO contains at least 2 bytes of data for reading and counts remain. If
a single byte of data remains in the FIFO, XDREQ asserted only when count mode is set and
the remaining count number is "1."
To describe a typical device operation, the ForceNAK bit is automatically set to "1" to return
a NAK response in the count mode reading operation when data exceeding the count number
set in the DMA_Count_HH,HL,LH,LL registers remains in the FIFO for the endpoint to
which that DMA is connected. Similarly, if a short packet is received from the USB, the
ForceNAK bit is automatically set to "1," and the corresponding endpoint NAK response is
returned unless the DisAF_NAK_Short bit is set.
If byte boundaries are formed when reading an odd number of bytes, use FIFO clear to clear
the byte boundaries before the next transfer. For example, to transfer data every 31 bytes
from the USB and read data every 31 bytes from the DMA, (1) receive 31 bytes of data from
the USB (ForceNAK is set here and the corresponding endpoint returns a NAK response), (2)
read 31 bytes of data from the DMA, (3) clear the FIFO, clear the ForceNAK, permit receipt
from the USB, then repeat these steps.
"1" can be read in the DMA_Control.DMA_Running bit until the operation halts.
[Operation stop]
The following two conditions must be met to stop an operation.
• DMA transfer must be complete for the count number set in the
DMA_Count_HH,HL,LH,LL registers.
• "1" is written to the DMA_Control.DMA_Stop bit.
XDREQ is negated while the last access strobe signal is being asserted when the transfer is
stopped by the DMA_Count_HH,HL,LH,LL registers.
When a transfer is stopped by the DMA_Stop bit, internal chip operations are stopped using
the synchronous register access write timing, and XDREQ is negated. To stop the DMA
using the DMA_Stop bit, first stop the CPU DMAC (master).
Fig. 1-83 shows the operational timing for starting transfers in count mode and the DMA
transfer ending once the preset number of counts have been transferred.
EPSON
S2R72V18 Technical Manual (Rev.1.00) 173