Cpu_Config (Cpu Configuration) - Epson S2R72V18 Technical Manual

3. Register Details
3.1.79 075h CPU_Config (CPU Configuration)
Base Address: Port0=000h, Port1=200h
Mode Ofst Adrs Register Name
Device 075h CPU_Config
/ Host
This register is a common register mirrored at Port 0 and Port 1.
It sets the LSI operating mode.
This bit can be accessed even in SLEEP state.
Bit7 IntLevel
This sets the XINT logic level.
0: Negative logic
1: Positive logic
Bit6 IntMode
This sets the XINT output mode.
0: 1/0 mode
1: Hi-z/0 mode
Bit5 DREQ_Level
This sets the XDREQ logic level.
0: Negative logic
1: Positive logic
Bit4 DACK_Level
This sets the XDACK logic level.
0: Negative logic
1: Positive logic
256
R/W Bit Symbol
R/W 7: IntLevel
R/W 6: IntMode
R/W 5: DREQ_Level
R/W 4: DACK_Level
R/W 3: CS_Mode
R 2: CPU_Endian
R 1: BusMode
R 0: Inisialized
EPSON
Description
0: Low Active 1: High Active
0: 1/0 mode 1: Hi-z/0 mode
0: Low Active 1: High Active
0: Low Active 1: High Active
0: DACK mode 1: CS mode
0: Do nothing 1: Bus Swap
0: XWRH/L mode 1: XBEH/L mode
0: N/A 1: Initialized
S2R72V18 Technical Manual (Rev.1.00)
Reset
01h