Page 1 S2R72V18 Technical Manual Rev.1.00...
Page 2 Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products.
Page 3 Scope This document applies to the S2R72V18 USB 2.0 device/host controller LSI.
Page 4: Table Of Contents
Bulk-Only Support ......................20 1.3.6.1 CBW Support ....................... 21 1.3.6.2 CSW Support ....................... 22 1.3.7 Cable Negotiation Function (Auto Negotiator) ..............23 1.3.7.1 Auto Negotiator ......................24 1.3.7.1.1 DISABLE ......................24 1.3.7.1.2 IDLE........................24 1.3.7.1.3 WAIT_TIM3US...................... 24 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 5 SETUP Transaction...................... 56 1.4.3.2 Bulk OUT Transaction ....................57 1.4.3.3 Interrupt OUT Transaction .................... 59 1.4.3.4 Isochronous OUT Transaction..................60 1.4.3.5 Bulk IN Transaction ...................... 61 1.4.3.6 Interrupt IN Transaction....................63 1.4.3.7 Isochronous IN Transaction..................65 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 6 If a Correct Device Chirp is Detected ............102 1.4.10.2.4.2 If an Error Device Chirp is Detected ............. 104 1.4.10.2.5 Port Error Detection .................... 105 1.4.10.3 Individual Host State Management Support Function Explanations ......106 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 7 1.4.10.3.10.1 If HS Device is Connected................147 1.4.10.3.10.2 If FS or LS Device is Connected ..............148 1.4.10.3.11 GoSUSPENDtoOP ..................... 149 1.4.10.3.12 GoRESUMEtoOP ....................151 Power Management Functions .................... 152 1.5.1 SLEEP........................... 153 1.5.2 ACTIVE ......................... 153 FIFO Management ......................154 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 8 Count Mode (Write) .................... 171 1.7.3.2.4 Count Mode (Read) .................... 173 1.7.3.2.5 Free-run Mode (Write) ..................175 1.7.3.2.6 Free-run Mode (Read) ..................175 1.7.3.2.7 REQ Assert Count Option (Write) ............... 176 1.7.3.2.8 REQ Assert Count Option (Read) ............... 177 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 9 Port0:01Fh / Port1:21Fh HostDeviceSel (Host Device Select) ........232 3.1.22 Port0:020h / Port1:220h FIFO_Rd_0 (FIFO Read 0) ..........233 3.1.23 Port0:021h / Port1:221h FIFO_Rd_1 (FIFO Read 1) ..........233 3.1.24 Port0:022h / Port1:222h FIFO_Wr_0(FIFO Write 0) ........... 234 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 10 Port0:054h / Port1:254h RAM_Rd_14 (RAM Read 14) ..........244 3.1.57 Port0:055h / Port1:255h RAM_Rd_15 (RAM Read 15) ..........244 3.1.58 Port0:056h / Port1:256h RAM_Rd_16 (RAM Read 16) ..........244 3.1.59 Port0:057h / Port1:257h RAM_Rd_17 (RAM Read 17) ..........244 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 11 (AREA 0 End Address High, Low) ................. 261 3.1.88 Port0:086h-087h / Port1:286h-287h AREA1EndAdrs_H,L (AREA 1 End Address High, Low) ................. 261 3.1.89 Port0:08Ah-08Bh / Port1:28Ah-28Bh AREA2EndAdrs_H,L (AREA 2 End Address High, Low) ................. 261 EPSON viii S2R72V18 Technical Manual (Rev.1.00)
Page 12 Port0:0C3h / Port1:N/A D_BulkIntEnb (Device Bulk Interrupt Enable)......283 3.2.14 Port0:0C4h / Port1:N/A D_EPrIntEnb (Device EPr Interrupt Enable) ......284 3.2.15 Port0:0C5h / Port1:N/A D_EP0IntEnb (Device EP0 Interrupt Enable) ......285 3.2.16 Port0:0C6h / Port1:N/A D_EPaIntEnb (Device EPa Interrupt Enable) ......286 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 13 Port0:110h-111h / Port1:N/A D_EPdMaxSize_H,L (Device EPd Max Packet Size High, Low) ............... 310 3.2.48 Port0:118h-119h / Port1:N/A D_EPeMaxSize_H,L (Device EPe Max Packet Size High, Low) ............... 310 3.2.49 Port0:0FAh / Port1:N/A D_EPaConfig (Device EPa Configuration)......312 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 14 Port0:155h / Port1:355h H_CH0IntEnb(Host CH0 Interrupt Enable) ......340 3.3.16 Port0:156h / Port1:356h H_CHaIntEnb (Host CHa Interrupt Enable) ......341 3.3.17 Port0:157h / Port1:357h H_CHbIntEnb (Host CHb Interrupt Enable) ......342 3.3.18 Port0:158h / Port1:358h H_CHcIntEnb (Host CHc Interrupt Enable)......342 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 15 (Host CHa Bulk Only Transfer Support Control) ............369 3.3.49 Port0:19Bh / Port1:39Bh H_CHaBO_CSW_RcvSize (Host CHa Bulk Only Transfer Support CSW Receive Data Size)......... 371 3.3.50 Port0:19Ch / Port1:39Ch H_CHaBO_OUT_EP_Ctl (Host CHa Bulk Only Transfer Support OUT Endpoint Control) ........372 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 16 Port0:1A9h / Port1:3A9h H_CHbFuncAdrs (Host Channel b Function Address) ..384 3.3.78 Port0:1B9h / Port1:3B9h H_CHcFuncAdrs (Host Channel c Function Address)..384 3.3.79 Port0:1C9h / Port1:3C9h H_CHdFuncAdrs (Host Channel d Function Address) ..384 EPSON S2R72V18 Technical Manual (Rev.1.00) xiii...
Page 17 Port0:1BEh / Port1:3BEh H_CHcConditionCode (Host Channel c Condition Code)... 387 3.3.91 Port0:1CEh / Port1:3CEh H_CHdConditionCode (Host Channel d Condition Code).. 387 3.3.92 Port0:1DEh / Port1:3DEh H_CHeConditionCode (Host Channel e Condition Code).. 387 Appendix A: Connection to Little-endian CPU ................389 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 18: Functions
S2R72V18 USB Port 0 USB Port 1 Individual registers Individual registers Shared registers Shared registers FIFO FIFO PowerManagement PowerManagement Host/Device Host Fig. 1-1 Block image EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 19: 1.2 Usb Device/Host Selection
Indicates a change in the device port status VBUS_0 terminal state. VBUS terminal change USB_DeviceIntEnb(0).EnVBUS_Changed Permits/prevents assertion of the status enable MainIntStat.USB_DeviceIntStat bit by USB_DeviceIntStat.VBUS_Changed. VBUS terminal state D_USB_Status(0).VBUS Indicates the device port VBUS_0 terminal state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 20: Host Port Change Status
This status indicates that the DP terminal (DP_0, DP_1) or DM terminal (DM_0, DM_1) state has changed for USB Port 0 Host mode or USB Port 1. Table 1-4 lists the registers for signal line change status. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 21 (5) The line state changes from SE0. A signal line change status is issued if a device is connected to the host port. (6) Check the signal line change status. (7) Clear the signal line change status. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 22 These settings are automatically set by the hardware to suit the host state after the firmware sets appropriate codes in the host state change execution register. For details, refer to “1.4.10 Host State Management Support Function.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 23: 1.3 Usb Device Control
Specifies the FIFO address corresponding to AREAx{x=0-5}EndAdrs_H,L the AREA0 area. The FIFO area must be at least as large as the max packet size. FIFO linking AREAx{x=0-5}Join_1.JoinEP0CH0 Links endpoint EP0 to the FIFO area to allow data transfer for EP0. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 24 Specify and reserve the area address. The AREAx{x=0-5}EndAdrs_H,L areas should be at least as large as the linked endpoint maximum packet sizes. The FIFO size may affect transfer throughput. FIFO linking AREAx{x=0-5}Join_1 Links the FIFO areas to endpoints. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 25: Transactions
For an in endpoint, the firmware writes data to the FIFO using the CPU interface (DMA write or register write) and creates active data in the FIFO to enable continuous and automatic execution of the in transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 26 Indicates that a SETUP transaction has been performed. Transaction status D_EP0IntStat.OUT_ShortACK, Indicates transaction results. D_EP0IntStat.IN_TranACK, D_EP0IntStat.OUT_TranACK, D_EP0IntStat.IN_TranNAK, D_EP0IntStat.OUT_TranNAK, D_EP0IntStat.IN_TranErr, D_EP0IntStat.OUT_TranErr Descriptor reply data D_EP0IntStat.DescriptorCmp Indicates the completion of an automatic stage completion status descriptor response data stage. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 27: Setup Transactions
D_SETUP_Control.ProtectEP0 bit are also set. When the firmware has completed the endpoint EP0 settings and is ready to proceed to the next stage, the SETUP_Control.ProtectEP0 bit should be cleared and the corresponding direction ForceNAK bits cleared for the D_EP0ControlIN and D_EP0ControlOUT registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 28: Bulk/Interrupt Out Transactions
FIFO is not updated. If not all data was received for bulk or interrupt OUT transactions, a NAK response is returned for the transaction. OUT_TranNAK status notification (D_EPx{x=0,a-e}IntStat.OUT_TranNAK bit) is issued. The FIFO is not updated. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 29: Isochronous Out Transactions
If an error occurs for isochronous OUT transactions, the data is not received, and the FIFO is not updated. OUT_TranErr status notification (EPx{x=a-e}IntStat.OUT_TranErr bit) is issued. OUT_TranNAK status notification (EPx{x=a-e}IntStat.OUT_TranNAK bit) is issued if the data for one packet is not fully received for isochronous OUT transactions. The FIFO is not updated. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 30: Bulk/Interrupt In Transactions
IN transaction is possible. (c) The host returns an ACK response. The LSI sets the register set automatically on receiving the ACK, and issues a status to the firmware. DATA Host to Device Device to Host Fig. 1-4 IN transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 31: Isochronous In Transaction
IN-direction endpoints, a response is returned to the IN transaction with a zero length data packet, and IN_TranNAK status notification (EPx{x=a-e}IntStat.IN_TranNAK bit) is issued to the firmware. The FIFO is not updated, and the area is not freed. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 32: Ping Transactions
OUT-direction endpoint in this node. (b) The LSI returns an ACK response to the PING transaction if FIFO includes free space equivalent to the max packet size. Status information is issued to the firmware. PING Host to Device Device to Host Fig. 1-5 PING transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 33: Control Transfers
The transition to the status stage is triggered by the host issuing a transaction in the direction opposite to the data stage. The firmware should be used to monitor the OUT_TranNAK status (D_EP0IntStat.OUT_TranNAK bit) and serve as the trigger to transition from the data stage to the status stage. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 34: Setup Stage
EP0 set to the IN direction to transition to the data stage. If the request received has no data stage, the D_EP0Control register INxOUT bit should be set and endpoint EP0 set to the IN direction to transition to the status stage. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 35: Data Stage/Status Stage
D_EP0Control.ReplyDescriptor bit is cleared, and DescriptorCmp status notification (D_EP0IntStat.DescriptorCmp bit) is issued to the firmware. The firmware should perform the status stage if DescriptorCmp status is detected. For details of the descriptor area, refer to “1.6 FIFO Management.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 36: Bulk/Interrupt/Isochronous Transfers
(including data length zero packets) is received when the D_EPx{x=a-e}Control.DisAF_NAK_Short bit is cleared (initial value). The D_EPx{x=a-e}Control.ForceNAK bit should be cleared as soon as preparations are complete for the next data transfers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 37: In Transfer
While the bulk-only support function is enabled and CBW or CSW support is activated, packets are received (CBW) or sent (CSW) using the area assigned as the CBW or CSW area rather than the FIFO area normally assigned to the endpoint. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 38: Cbw Support
In this case, the D_BulkOnlyControl.GoCBW_Mode bit is not cleared, and CBW support continues. The D_BulkOnlyControl.GoCSW_Mode bit is not cleared here, even if set. The data received at the CBW area can be read out using the RAM_Rd function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 39: Csw Support
ACK, the next CBW will run, but a response is possible since CBW support is activated. CBW support will terminate CSW support. Data can be written to the CSW area with the RAM_WrDoor function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 40: Cable Negotiation Function (Auto Negotiator)
InChirp == 1 LineState == K State LineState == SE0 State CHK_ WAIT_ EVENT RSTEND irq_DetectReset == 1 RESUME state InChirp == 0 LineState != (SE0 || K)State irq_AutoNegoErr DetectSeq = start Fig. 1-8 Auto negotiator EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 41: Auto Negotiator
If a reset is determined, the event detection function is suspended and the WAIT_TIM3US state imposed. 1.3.7.1.3 WAIT_TIM3US This adjusts the time taken to run the HS Detection Handshake after reset detection. WAIT_CHIRP status is imposed after a preset time (approx. 3 µs) has elapsed. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 42: Wait_Chirp
The auto negotiator switches to CHK_EVENT state when InSUSPEND is cleared. To resume from suspend automatically with applications with the remote wakeup function enabled, set the D_NegoControl.SendWakeup bit while in this state and output FS-K for between 1 ms and 15 ms. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 43: Chk_Event
D_USB_Status.LineState[1:0] bit (note that it will be reset (see later) if “SE0” is detected). If “J” is still detected at the subsequent point T2, the D_SIE_IntStat.DetectSUSPEND bit is set and a USB suspend state is determined. The figure below illustrates the steps involved in running SLEEP during USB suspend. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 44 USB. (Set DisBusDetect to “1” before switching to SLEEP to prevent repeated detection of SUSPEND.) The internal clock stops completely. T5 < T4 + 10 µs Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 45: Suspend Detection In Fs Mode
The figure below illustrates the steps involved in running SLEEP during USB suspend. time XcvrSelect TermSelect DetectSUSPEND GoSLEEP DisBusDetect LineState[1:0] 'J' State Last DP / DM 'J' state Activity Internal clock Fully meet USB2.0 required frequency FS Mode SLEEP Fig. 1-10 Suspend timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 46 USB. (Set DisBusDetect to “1” before switching to SLEEP to prevent repeated detection of SUSPEND.) The internal clock stops completely. T5 < T4 + 10 µs Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 47: Reset Detection In Hs Mode
DetectRESET is set to “1,” and the LSI determines a transition T1 + 875 µs to reset. Sets DisBusDetect to “1” after detecting a reset command, then performs the HS Detection Handshake. Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 48: Reset Detection In Fs Mode
HS Reset T0 + 2.5 µs < T1 {T WTREV determines a transition to reset. Sets DisBusDetect to “1” after detecting a reset command, then performs an HS Detection Handshake. Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 49: Hs Detection Handshake
Reset is detected if a SLEEP command is issued during Suspend. For this reason, the PM_Control.GoACTIVE bit must always be set to “1” to operate the internal clock for the HS Detection Handshake. For detailed information on this procedure, refer to “1.5 Power Management Functions.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 50: When Connected To The Fs Host Downstream Port
Normal Normal Operation and NRZI ChirpCmp LineState[1:0] 'K' State 'J' State Device K DP / DM 'J' State Upstream No Downstream FS Mode Port Chirp Port Chirps Fig. 1-13 HS detection handshake timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 51 HS Reset T0 + 10 ms {T (Min)} DRST Normal operation in FS mode. Note: Brackets {} indicate names defined in the USB 2.0 standards. Note: Determine at 66,000 cycles (internal clock: 60 MHz) to generate minimum 1 ms Chirp K. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 52: When Connected To The Hs Host Downstream Port
HS termination is activated by the D_XcvrControl.TermSelect bit. The Chirp is normally approximately 800 mV when the D_XcvrControl.TermSelect bit is in FS mode and approximately 400 mV when the D_XcvrControl.TermSelect bit is in HS mode (same as for normal packets sent and received). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 53 HS Reset T0 + 10 ms {T (Min)} DRST Note: Brackets {} indicate names defined in the USB 2.0 standards. Note: Determine at 66,000 cycles (internal clock: 60 MHz) to generate minimum 1 ms Chirp K. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 54: If Reset During Sleep
NRZI LineState[1:0] 'K' State Device K DP / DM Internal clock Fully meet USB2.0 required frequency Look for Upstream PLL Powerup time downstream Port Chirp chirps Fig. 1-15 HS detection handshake timing from suspend EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 55 Note: Determine at 66,000 cycles (internal clock: 60 MHz) to generate minimum 1 ms Chirp K. Note: The situation in which the oscillator circuit is also stopped (Sleep state) is described later (PLL and OSC power-up time is required). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 56: Resume Issue
Note that this explanation addresses only the condition in which the mode before USB Suspend is HS mode. The normal FS mode is used after T5 if the mode before USB Suspend was FS mode, and there are no major sequence differences. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 57 RestoreCmp is set to “1.” The LSI automatically switches to HS T5 + 1.33 µs {2 Low-speed bit times} mode if the mode prior to USB Suspend was HS mode. Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 58: Resume Detection
D_XcvrControl.XcvrSelect and D_XcvrControl.TermSelect bits switch to the required mode (here, HS mode) when this is detected (no longer “K”), and the D_NegoControl.RestoreUSB bit is then cleared and the D_SIE_IntStat.RestoreCmp bit set. The D_SIE_IntEnb.EnRestoreCmp bit is set here. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 59 The LSI switches automatically to HS mode if the mode prior to T5 + 1.33 µs {2 Low-speed bit times} USB Suspend was HS mode. Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 60: Cable Attachment
(T3). The D_XcvrControl.TermSelect bit should be set to FS mode (T4) to switch to FS mode temporarily, since it should be assumed first that an FS device was connected. The host downstream port then sends a Reset (T5), and the HS Detection Handshake starts. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 61 “00.” Switches to FS mode. FS termination is enabled. A Reset is issued from the host downstream port. DisBusDetect T4 + 100 ms {T } < T5 ATTDB is set to “1.” Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 62: 1.4 Usb Host Control
(for OUT transfer) and reads data from the buffer (for IN transfer) until all IRP data has been processed. Concurrently, the hardware (channel) automatically divides IRPs into multiple transactions. Once transfer is complete, it notifies the firmware using an interrupt. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 63 Control transfer support function (1.4.4.3) can be used. Bulk transfer Bulk-only support function (1.4.8) can be used. CHb, CHc CHd, CHe Bulk transfer Audio class assist function can be used (1.4.9). Interrupt transfer Isochronous transfer EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 64: Dedicated Control Channel
For detailed information on FIFO area assignments, refer to “1.6 FIFO Management.” FIFO area join AREAn{n=0-5}Join_1.JoinEP0CH0 Joins channel CH0 to the FIFO area. Setup data H_CH0SETUP_x(x=0-7) Sets the 8-byte data to be sent by the setup transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 65: General Channels
Sets the quantity of data in bytes for the IRP H_CHx{x=a-e}TotalSize_HL, to be executed by each channel. H_CHx{x=a-e}TotalSize_LH, H_CHx{x=a-e}TotalSize_LL Token issue interval H_CHx{x=b-e}Interval_H, Sets the interval (period) for issuing tokens H_CHx{x=b-e}Interval_L for interrupt and isochronous transfer. (continued) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 66 The FIFO area size affects data transfer throughput. For detailed information on FIFO area assignments, refer to “1.6 FIFO Management.” FIFO area join AREAn{n=0-5}Join_1.JoinEPxCHx{x=a-e} Joins each channel to the FIFO area. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 67: Channel Usage Examples
HDD1 (for Ctl only) HDD1 HDD1 BulkIn (for Bulk 1) BulkOut BulkIn Bulkout (for Bulk/Int/Iso 1) (for Bulk/Int/Iso 2) (for Bulk/Int/Iso 3) (for Bulk/Int/Iso 4) Fig. 1-21 Channel usage example (with one storage device connected) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 68: With One Communication Device Connected
(Channel Resister) (for Ctl only) (for Bulk 1) BulkIn BulkIn (for Bulk/Int/Iso 1) Bulkout BulkOut (for Bulk/Int/Iso 2) IntIn IntIn (for Bulk/Int/Iso 3) (for Bulk/Int/Iso 4) Fig. 1-22 Channel usage example (with one communication device connected) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 69: With One Human Interface Device Connected
(for Ctl only) HID1 (for Bulk 1) BulkIn (for Bulk/Int/Iso 1) Bulkout (for Bulk/Int/Iso 2) HID1 IntIn IntIn (for Bulk/Int/Iso 3) (for Bulk/Int/Iso 4) Fig. 1-23 Channel usage example (with one human interface device connected) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 70: With Two Storage Devices Connected Via A Hub
(for Bulk/Int/Iso 1) Channel-C Hub1 (for Bulk/Int/Iso 2) Hub1 Channel-D USB Memory (for Bulk/Int/Iso 3) Hub2 Hub2 Channel-E (for Bulk/Int/Iso 4) BulkIn Bulkout Fig. 1-24 Channel usage example (with two storage devices connected via a hub) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 71: Scheduling
Table 1-24 shows the control items for general channel (CHa, CHb, CHc, CHd, CHe) scheduling control. Table 1-24 General channel scheduling settings Item Register/bit Description Execute transfer H_CHx{x=a-e}Config_0.TranGo Sets transfer execution for each channel. Performs the transfer in accordance with the channel settings. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 72: Transactions
Table 1-26 shows the control items and status involved in general channel (CHa, CHb, CHc, CHd, CHe) transaction control. Table 1-26 General channel control items and status Item Register/bit Description Transaction status H_CHx{x=a-e}IntStat.TotalSizeCmp, Indicates the transaction results. H_CHx{x=a-e}IntStat.TranACK, H_CHx{x=a-e}IntStat.TranErr, H_CHx{x=a-e}IntStat.ChangeCondition Transaction condition H_CHx{x=a-e}ConditionCode Indicates transaction result specifics. code EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 73: Setup Transaction
0 in the destination node. (b) The LSI then sends an 8-byte data packet. (c) The LSI automatically sets the corresponding register on receiving the ACK and issues status information to the firmware. SETUP DATA Host to Device Device to Host Fig. 1-25 SETUP transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 74: Bulk Out Transaction
OUT token addressed to the OUT-direction endpoint at the destination node. (b) The LSI then sends a data packet no larger than the maximum packet size. (c) The LSI automatically sets the corresponding register on receiving ACK and issues status information to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 75 1. Functions DATA Host to Device Device to Host Fig. 1-26 OUT transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 76: Interrupt Out Transaction
TranErr status notification (H_CHx{x=b-e}IntStat.TranErr bit) is issued to the firmware. Although Retry processing is performed, H_CHx{x=b-e}Control.TranGo is automatically cleared to end the transfer if three successive errors occur, and then a ChangeCondition status notification (H_CHx{x=b-e}IntStat.ChangeCondition bit) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 77: Isochronous Out Transaction
The LSI automatically sets the corresponding register after sending the data packet, and issues status information to the firmware. DATA Host to Device Device to Host Fig. 1-27 Isochronous OUT transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 78: Bulk In Transaction
(H_CHx{x=a-e}IntStat.TranErr bit) is issued to the firmware. The FIFO is not updated. If an error occurs for which the condition code (H_CHx{x=a-e}ConditionCode) is set to “RetryError,” retry processing is performed. If three successive errors occur, EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 79 (c) The LSI returns an ACK response, automatically sets the corresponding register, and issues status information to the firmware. DATA Host to Device Device to Host Fig. 1-28 IN transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 80: Interrupt In Transaction
If a timeout error, CRC error, bit stuffing error, or PID error (including unforeseen PID) occurs for the interrupt IN transaction, no response is returned. The condition code (H_CHx{x=b-e}ConditionCode) is set to “RetryError,” and a TranErr status notification (H_CHx{x=b-e}IntStat.TranErr bit) is issued to the firmware. The FIFO is not updated. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 81 If an error occurs for which the condition code (H_CHx{x=b-e}ConditionCode) is set to “RetryError,” retry processing is performed at the next cycle. If three successive errors occur, H_CHx{x=b-e}Control.TranGo is automatically cleared to end the transfer, and a ChangeCondition status notification (H_CHx{x=b-e}IntStat.ChangeCondition bit) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 82: Isochronous In Transaction
IN transaction. The LSI automatically sets the corresponding register after receiving the data packet, and issues status information to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 83 1. Functions DATA Host to Device Device to Host Fig. 1-29 Isochronous IN transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 84: Ping Transaction
PING token addressed to the OUT-direction endpoint existing in the node. (b) The device returns an ACK response to the PING transaction if there is space equivalent to the maximum packet size at the endpoint. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 85 1. Functions PING Host to Device Device to Host Fig. 1-30 PING transaction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 86: Low-Speed (Ls) Transaction
(c) The LSI automatically sets the corresponding register after receiving the ACK and issues status information to the firmware. DATA Host to Device Device to Host Fig. 1-31 OUT transaction with preamble attached EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 87 It then automatically sets the corresponding register and issues status information to the firmware. DATA Host to Device Device to Host Fig. 1-32 IN transaction with preamble attached EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 88: Split Transaction
The FIFO is not updated. Retry processing is performed. If three successive errors occur for control, bulk, or interrupt transfers, H_CHx{x=0,a-e}Control.TranGo is automatically cleared to end the transfer, and a ChangeCondition status notification (H_CHx{x=0,a-e}IntStat.ChangeCondition bit) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 89: Control Transfers
(c) The host issues an IN transaction and performs the status stage. Control transfers without a data stage are performed without the data stage shown in this example. Host to Device Device to Host Fig. 1-34 Control transfer with data stage in OUT direction EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 90: Setup Stage
If the stage is in the OUT direction, set the transaction type (H_CH0Config_1.TID) to “OUT,” set the other basic setting registers appropriately and execute the transaction. For the status stage, the IRP data quantity (H_CH0TotalSize_H,L) should be set to “0x0” before executing the transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 91: Control Transfer Support Function
(4) Set the control transfer support execute (H_CTL_SupportControl.CTL_SupportGo). The control transfer stage (H_CTL_SupportControl.CTL_SupportState) value is written to the H_CTL_SupportControl register here as “Idle(00b).” (5) Execute the SETUP transaction using the SETUP register data (8 bytes) (SETUP stage). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 92 ChangeCondition status notification (H_CH0IntStat.ChangeCondition bit) is issued. If control transfer is aborted, control transfer support execution (H_CTL_SupportControl.CTL_SupportGo) is cleared. Status notification is issued once the control transfer abort processing is completed. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 93 Control transfer H_CH0IntStat.CTL_SupportCmp Indicates control transfer execution results execution results H_CH0IntStat.CTL_SupportStop using the control transfer support function. Transaction status H_CH0IntStat.TotalSizeCmp, Indicates transaction results. H_CH0IntStat.TranACK, H_CH0IntStat.TranErr, H_CH0IntStat.ChangeCondition Transaction condition H_CH0ConditionCode.ConditionCode Indicates transaction result specifics. code EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 94: Bulk/Interrupt/Isochronous Transfers
When TotalSize reaches zero, H_CHx{x=0,a-e}Config_0.TranGo is automatically cleared to end the transfer, and a TotalSizeCmp status notification (H_CHx{x=0,a-e}IntStat.TotalSizeCmp bit) is issued to the firmware. OUT transfers can be controlled in this way without controlling individual transactions with firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 95: In Transfers
FIFO area can be read in the order received by executing a DMA sequence for the CPU interface. The amount of FIFO data remaining can be checked using the DMA_Remain_H,L registers. If the FIFO becomes empty, the CPU interface pauses DMA automatically to control the flow. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 96: Zero Length Packet Automatic Issuing Function
OUT transaction is executed using a zero-length packet. If this transaction ends normally, H_CHx{x=a-e}Config_0.TranGo is automatically cleared to end the transfer, and a TotalSizeCmp status notification (H_CHx{x=a-e}IntStat.TotalSizeCmp) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 97: Bulk-Only Support Function
Bulk Completion confirmation Fig. 1-37 Bulk-only support function control Host Host Controller (Channel Resister) Bulk (Bulk-only) Completion confirmation Bulk DATA Completion confirmation Bulk Completion confirmation Fig. 1-38 Control when not using bulk-only support function (reference) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 98 IN transaction. The IN-direction data transport also ends when a short packet is received for the IN transaction. • If the CBW data dCBWDataTransferLength value is 0x00000000, no data transport is performed. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 99 (H_CHaIntStat.BO_SupportStop). The transport for which an error occurred is indicated by the transport state (H_CHaBO_SupportControl.BO_TransportState). The condition code (H_CHaConditionCode) is set appropriately, and a ChangeCondition status notification (H_CHaIntStat.ChangeCondition bit) issued. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 100 For detailed information on transaction errors, refer to “1.4.3 Transactions.” For detailed information on FIFO CBW and CSW areas, refer to “1.6 FIFO Management.” For detailed information on DMA, refer to “1.7.3.2 DMA0/DMA1(DMA ch.0 / ch.1).” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 101 Indicates the transport state for which an error occurred if stopped due to an error. Status transport H_CSW_RcvDataSize Indicates the data quantity received for received data quantity the status transport. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 102: Audio Class Assist Function
Item Register/bit Description Audio class assist H_CHx{x=b-e}Config_1.Audio441 Enables the audio class assist function. This function function can be used only for OUT-direction isochronous transfers. Do not set this bit to “1” when using other transfers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 103: Host State Management Support Function
GoRESUME (Trigger: DetectRmtWkup or Nothing) SUSPEND GoRESET Transition conditions (Trigger: Noting) (Trigger: Interrupt forming trigger) Fig. 1-39 Host state transition diagram Tables 1-31 and 1-32 show the host state management support function settings and status. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 104 Device chirp normal H_SIE_IntStat_0.DetectDevChirpOK Indicates that the chirp signal from the detection status device is normal. Device chirp error detection H_SIE_IntStat_0.DetectDevChirpNG Indicates an error in the chirp signal from the status device. (continued) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 105: Idle
• Immediately stops the USB host transaction execute function. • Sets the port to FS mode and “NonDriving.” • Switches off VBUSEN_A. • Disables all detection functions, including connection detection, disconnection detection, remote wakeup detection, and device chirp detection. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 106: Wait_Connect
However, if a disconnection is detected, the disconnection detection function is automatically disabled and connection detection automatically repeated. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 107: Disabled
• The port is set to HS mode and “NormalOperation” (reset signal SE0 is driven for the USB cable signal). • The connection detection, disconnection detection, and remote wakeup detection functions are disabled. • The device chirp detection function is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 108 Reset completion status notification (H_SIE_IntStat_1.ResetCmp) is issued to the firmware. (4) If the connected device is LS The port is set to LS mode after issuing the USB reset for the specified timeframe. Reset completion status notification (H_SIE_IntStat_1.ResetCmp) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 109: Operational
• Suspend change completion status notification (H_SIE_IntStat_1.SuspendCmp) is issued. Remote wakeup detection status notification (H_SIE_IntStat_0.DetectRmtWkup) is then issued to the firmware on detection of a remote wakeup signal (“K” for at least 2.5 µs) if the remote wakeup receipt permission (H_NegoControl_1.RmtWkupDetEnb) is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 110: Resume
A resume signal (“K”) is issued for the specified duration. When the resume signal has been issued, the port reverts to the mode setting prior to entering “SUSPEND,” and returns to “NormalOperation.” Resume completion status notification (H_SIE_IntStat_1.ResumeCmp) is issued to the firmware. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 111: Detection Functions
VBUSFLG_A VBUS_Err VBUSEN_A VBUS_State Don't care XcvrSelect[1:0] TermSelect NonDriving OpMode[1:0] Don't care PortSpeed[1:0] Don't care LineState[1:0] Don't care Don't care DP / DM VBUS VBUS error VBUS off normal Fig. 1-40 VBUS error detection timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 112 VBUSFLG_A (external USB power switch error occurrence 0 (reference) flag) input terminal changes to L (error). VBUS error detection status notification (USB_HostIntStat.VBUS_Err) is issued. (H/W) Write 0x01 to change to “IDLE” state after writing 0x80 to (reference) H_NegoControl_0. (F/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 113: Disconnect Detection
Table 1-34 Disconnect detection timing values (HS mode) Timing Description Value Parameter Device is disconnected. 0 (reference) Disconnect detection status notification (H_SIE_IntStat_0.DetectDiscon) is issued. (H/W) Set the host state change execute (reference) (H_NegoControl_0.AutoMode) to “GoWAIT_CONNECT.” (F/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 114: If Fs Or Ls Device Is Disconnected
Value Parameter Device is disconnected. 0 (reference) Disconnect detection status notification T0 + 2.5 µs< T1 {T DDIS (H_SIE_IntStat_0.DetectDiscon) is issued. (H/W) Set the host state change execute No specifications (reference) (H_NegoControl_0.AutoMode) to “GoWAIT_CONNECT.” (F/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 115: Remote Wakeup Detection
Disable BS and NRZI PortSpeed[1:0] LineState[1:0] 'J' State 'K' State DP / DM 'J' State 'K' State FS Mode Downstream Resume Upstream Resume Device is suspended (FS Mode) Fig. 1-43 Remote wakeup timing (HS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 116 (H_NegoControl_0.AutoMode) is set to “GoRESUME.” (F/W) T3 (reference) The host starts sending the resume signal (“K”). (H/W) T3 < T0 + 1 ms {T URSM Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 117: If Fs Device Is Connected
T2 < T1 + 900 µs (reference) set to “GoRESUME.” (F/W) The host starts sending the resume signal (“K”). (H/W) T3 < T0 + 1 ms {T URSM (reference) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 118: If Ls Device Is Connected
T2 < T1 + 900 µs (reference) set to “GoRESUME.” (F/W) The host starts sending the resume signal (“K”). (H/W) T3 < T0 + 1 ms {T URSM (reference) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 119: Device Chirp Detection Function
(6) The device chirp detection function is disabled if a device chirp is detected (T3). time HostState[2:0] Don't care RESET DetectDevChirpOK XcvrSelect[1:0] HS/FS TermSelect OpMode[1:0] Normal Operation LineState[1:0] 'J' State DP / DM Device K Reset Upstream Port Chirp Fig. 1-46 Device chirp timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 120 } < T3 < The device chirp detection function is disabled. T0 + 7.0 ms {T UCHEND Device chirp normal detection status notification (DetectDevChirpOK) is issued. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 121: If An Error Device Chirp Is Detected
T1 + 2.5 µs {T } < T2 FILT Device chirp error detection status notification T0 + 7 ms {T } < T3 UCHEND (DetectDevChirpNG) is issued. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 122: Port Error Detection
(1) Set H_NegoControl_0.AutoMode to “GoDISABLED.” (2) Set ChipReset.ResetMTM to “1” and reset the transceiver macro. (3) Set ChipReset.ResetMTM to “0” after at least three cycles have elapsed with a 60 MHz clock and cancel the transceiver macro reset. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 123: Individual Host State Management Support Function Explanations
(8) Disables all detection functions, including connect detection, disconnect detection, remote wakeup detection, and device chirp detection. time HostState[2:0] Don't care IDLE VBUSEN_A VBUS_State XcvrSelect[1:0] TermSelect OpMode[1:0] NonDriving LineState[1:0] DP / DM Fig. 1-48 GoIDLE timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 124 Sets the transceiver selection to FS mode. Sets the terminal selection to FS mode. Sets the operating mode to “NonDriving.” Immediately stops the transaction execute function. Disables connect detection, disconnect detection, remote wakeup detection, and device chirp detection. (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 125: Gowait_Connect
(T4). If a disconnection is detected during this period, the disconnect detection function is disabled and connect detection repeated from step (8). Disconnect detection status notification (H_SIE_IntStat_0.DetectDiscon) is not issued. (12) Disables the disconnect and connect detection functions (T4). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 126 DCNN Issues connect detection status notification (DetectCon). T3 + 100 ms {T } < T4 ATTDB Disables the disconnect and connect detection functions. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 127: If An Ls Device Is Connected
(H_XcvrControl.XcvrSelect) and port speed (H_NegoControl_1.PortSpeed[1:0]) are both set to “FS,” and connect detection is repeated from step (8). Disconnect detection status notification (H_SIE_IntStat_0.DetectDiscon) is not issued. (14) Disables the disconnect and connect detection functions (T4). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 128 Issues connect detection status notification (DetectCon). (H/W) T3 + 100 ms {T } < T4 ATTDB Disables the disconnect and connect detection functions. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 129: Godisabled
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] SE0/'J' State 'J' State DP / DM Last Activity 'J' State HS Mode FS Mode Device is suspended (FS Mode) Fig. 1-51 Disabled timing (HS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 130 } < WTREV T1 + 3.125 ms Enables the disconnect detection function. (H/W) T1 + 4 ms < T3 Issues disabled change completion status. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 131: If An Fs Device Is Connected
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] 'J' / 'K' State 'J' State DP / DM Last Activity 'J' State FS Mode Device is suspended (FS Mode) Fig. 1-52 Disabled timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 132 } < WTREV T1 + 3.125 ms Enables the disconnect detection function. T1 + 4 ms < T3 Issues disabled change completion status. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 133: If An Ls Device Is Connected
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] 'J' / 'K' State 'J' State DP / DM Last Activity 'LS_J' State LS Mode Device is suspended (LS Mode) Fig. 1-53 Disabled timing (LS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 134 } < WTREV T1 + 3.125 ms Enables the disconnect detection function. T1 + 4 ms < T3 Issues disabled change completion status. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 135: Goreset
(9) The host starts output of “Chirp J” switching from “Chirp K” (T4). (10) The host starts output of “Chirp K” switching from “Chirp J” (T5). The host then alternately outputs “Chirp K” and “Chip J.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 136 OpMode[1:0] Normal Operation Normal Operation Disable BS and NRZI PortSpeed[1:0] LineState[1:0] 'J' State DP / DM Device K Reset Operational Upstream Downstream Port Chirp Port Chirp Device HS Mode Fig. 1-54 Reset timing (HS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 137 T10 + 120 µs < T11 < T10 + 130 µs (reference) T8 + 100 µs {T } < T11 < DCHSE0 T8 + 500 µs {T DCHSE0 Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 138: Error Device Chirp Detection
(H_SIE_IntStat_0.DetectDevChirpNG) is issued (T2). (7) Disables the device chirp detection function (T2). (8) Reset is ended (T3). (9) Issues reset completion status notification (H_SIE_IntStat_1.ResetCmp) (T3). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 139 Reset ends. Issues reset completion status notification T2 + 50 ms {T } < T3 DRSTR (ResetCmp). (H/W) Sets H_NegoControl_0.AutoMode to “GoDISABLED.” (F/W) (reference) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 140: If Chirp Completion Disable (H_Negocontrol_1.Dischirpfinish) Setting Is 1
(10) The host starts output of “Chirp J” switching from “Chirp K” (T5). (11) The host starts output of “Chirp K” switching from “Chirp J” (T6). The host then alternately outputs “Chirp K” and “Chip J.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 141 Disable BS and NRZI PortSpeed[1:0] LineState[1:0] 'J' State DP / DM Device K Reset Operational Upstream Downstream Port Chirp Port Chirp Device HS Mode Fig. 1-56 Detect device chirp NG timing (with chirp completion disable set to 1) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 142 T11 + 120 µs < T12 < T11 + 130 µs (reference) T9 + 100 µs {T } < T12 < DCHSE0 T9 + 500 µs {T DCHSE0 Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 143: Resetting For Fs Device
(9) Issues reset completion status (H_SIE_IntStat_1.ResetCmp) (T3). time HostState[2:0] Don't care RESET OPERATIONAL ResetCmp XcvrSelect[1:0] HS/FS TermSelect OpMode[1:0] Disable BS and NRZI Normal Operation Normal Operation PortSpeed[1:0] HS/FS LineState[1:0] Driven DP / DM 'J' State Fig. 1-57 Reset timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 144 (F/W) Sends the first SOF. (H/W) T4 + 0.9 ms < T5 < T4 + 1.1 ms (reference) (T5 < T2 + 3 ms) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 145: Resetting For Ls Device
(F/W) Sends the first KeepAlive. (H/W) T4 + 0.9 ms < T5 < T4 + 1.1 ms (reference) (T5 < T2 + 3 ms) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 146: Gooperational
0 (reference) (F/W) Sends the first SOF (HS/FS) or KeepAlive (LS). T0 + 120 µs < T1 (HS) < T0 + 130 µs T0 + 0.9 ms < T1 (FS,LS) < T0 + 1.1 ms EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 147: Gosuspend
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] SE0/'J' State 'J' State DP / DM Last Activity 'J' State HS Mode FS Mode Device is suspended (FS Mode) Fig. 1-60 Suspend timing (HS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 148 } < T3 WTRSM Enables the remote wakeup detection function if remote wakeup receipt permission is enabled. Issues suspend change completion status notification. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 149: If Fs Device Is Connected
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] 'J' / 'K' State 'J' State DP / DM Last Activity 'J' State FS Mode Device is suspended (FS Mode) Fig. 1-61 Suspend timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 150 } < T3 WTRSM Enables the remote wakeup detection function if remote wakeup receipt permission is enabled. Issues suspend change completion status notification. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 151: If Ls Device Is Connected
XcvrSelect[1:0] TermSelect Normal Operation Power Down OpMode[1:0] PortSpeed[1:0] LineState[1:0] 'J' / 'K' State 'J' State DP / DM Last Activity 'LS_J' State LS Mode Device is suspended (LS Mode) Fig. 1-62 Suspend timing (LS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 152 } < T3 WTRSM Enables the remote wakeup detection function if remote wakeup receipt permission is enabled. Issues suspend change completion status notification. (H/W) Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 153: Goresume
DisBS & NRZI Normal Operation OpMode[1:0] PortSpeed[1:0] LineState[1:0] 'J' State 'K' State uSOF DP / DM 'J' State 'K' State FS Mode HS Mode Downstream Resume Device is suspended Fig. 1-63 Resume timing (HS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 154 Issues the first micro SOF. (H/W) T5 < T1 + 3 ms (reference) T4 + 120 µs < T5 < T4 + 130 µs Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 155: If Fs Device Is Connected
PortSpeed[1:0] LineState[1:0] 'J' State 'K' State 'J' State 'J' / 'K' State Driven 'J' State 'K' State DP / DM 'J' State FS Mode Downstream Resume Device is suspended Fig. 1-64 Resume timing (FS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 156 Sets the operating mode to “NormalOperation.” (H/W) Issues the first SOF. (H/W) T4 < T1 + 3 ms (reference) T3 + 0.9 ms < T4 < T3 + 1.1 ms Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 157: If Ls Device Is Connected
'J' State 'K' State 'J' State 'J' State Keep Driven 'LS_J' State 'LS_K' State Alive DP / DM LS_J 'LS_J' State 'LS_J' State LS Mode Downstream Resume Device is suspended Fig. 1-65 Resume timing (LS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 158 Sets the operating mode to “NormalOperation.” (H/W) Issues the first KeepAlive. (H/W) T4 < T1 + 3 ms (reference) T3 + 0.9 ms < T4 < T3 + 1.1 ms Note: Brackets {} indicate names defined in the USB 2.0 standards. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 159: Gowait_Connecttodis
Sets H_NegoControl_0.AutoMode to 0 (reference) “GoWAIT_CONNECTtoDIS.” (F/W) Performs the same processing performed for “GoWAIT_CONNECT.” (H/W) Detects connection and issues connect detection status notification. Performs the same processing performed for “GoDISABLED.” (H/W) Issues disabled completion status. (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 160: Gowait_Connecttoop
“1.4.10.3.3 GoDISABLED,” “1.4.10.3.4 GoRESET,” and “1.4.10.3.5 GoOPERATIONAL,” respectively. For detailed information on procedures and timing when an error (disconnection, VBUS error, or device chirp error) is detected in midcourse, refer to “1.4.10.2.2 Disconnect Detection” and “1.4.10.2.1 VBUS Error Detection.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 161 Issues disabled completion status. Performs the same processing performed for “GoRESET.” (H/W) Detects the device chirp and issues device chirp normal detection status. (H/W) Issues reset completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 162: If Fs Or Ls Device Is Connected
VBUS error) is detected in midcourse, refer to “1.4.10.2.2 Disconnect Detection” and “1.4.10.2.1 VBUS Error Detection,” respectively. time HostState[2:0] Don't care WAIT_CONNECT RESET OPERATIONAL DISABLED DetectCon DisabledCmp DetectDevChirpOK DetectDevChirpNG ResetCmp Fig. 1-68 GoWAIT_CONNECTtoOP timing (FS or LS mode) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 163 Issues disabled completion status. Performs the same processing performed for “GoRESET.” (H/W) No device chirp normal/error detection status notification issued, since no device chirp detected. (H/W) Issues reset completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 164: Goresettoop
0 (reference) Performs the same processing performed for “GoRESET.” (H/W) Detects the device chirp and issues device chirp normal detection status notification. (H/W) Issues reset completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 165: If Fs Or Ls Device Is Connected
0 (reference) Performs the same processing performed for “GoRESET.” (H/W) No device chirp normal/error detection status notification issued, since no device chirp detected. (H/W) Issues reset completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 166: Gosuspendtoop
(5) Performs the same processing performed for “GoRESUME” (T2). (6) Issues resume completion status (H_SIE_IntStat_1.ResumeCmp) (T3). (7) Performs the same processing performed for “GoOPERATIONAL” (T3). time HostState[2:0] OPERATIONAL SUSPEND RESUME OPERATIONAL SuspendCmp DetectRmtWkup ResumeCmp Fig. 1-71 GoSUSPENDtoOP timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 167 Issues suspend change completion status notification. (H/W) Detects the remote wakeup and issues remote wakeup detection status notification. Performs the same processing performed for “GoRESUME.” (H/W) Issues resume completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 168: Goresumetoop
Table 1-65 GoRESUMEtoOP timing values Timing Description Value Parameter Sets H_NegoControl_0.AutoMode to “GoRESUMEtoOP.” (F/W) 0 (reference) Performs the same processing performed for “GoRESUME.” (H/W) Issues resume completion status. Performs the same processing performed for “GoOPERATIONAL.” (H/W) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 169: 1.5 Power Management Functions
This means operations will no longer be correctly performed. GoACTIVE S0: SLEEP S1: SNOOZE S2: ACTIVE GoSLEEP Port 0 GoACTIVE S0: SLEEP S1: SNOOZE S2: ACTIVE GoSLEEP Port 1 Fig. 1-73 Power management state transitions EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 170: Sleep
WakeUpTim_H,L registers. The WakeUpTim_H,L registers allow asynchronous access and can be read from or written to even in the SLEEP state. The USB host circuit operates in this state, since it requires a 480 MHz SCLK480. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 171: 1.6 Fifo Management
“1.6.3.1 CBW Area (for USB device).” This CBW area is also used for the CHa bulk-only support function with USB hosts. For detailed information on actual usage procedures, refer to “1.6.3.2 CBW Area (for USB host).” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 172: Descriptor Area
The RAM_WrAdrs_H,L register values are updated by the quantity of data written for each write cycle. This enables continuous writing to the RAM_WrDoor_0,1 registers when writing data to continuous addresses. Note that the RAM_WrDoor_0,1 registers allow writing only. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 173: Executing Data Stage (In) With Descriptor Area
(0x0000) is written to the RAM_WrAdrs_H,L registers, then 31 bytes of valid data are written via the RAM_WrDoor_0,1 registers. The CBW area holds 32 bytes; there should be no issue with leakage into other areas, even when 32 bytes are written in word access. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 174: Csw Area
RAM_Rd_00 to RAM_Rd_1F after checking the RAM_RdCmp bit. The data read out is stored in sequence from RAM_Rd_00. The RAM_Rd register values will be invalid beyond the preset size if the size set in the RAM_RdCount register is smaller than 32. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 175: Ram Access (Ram_Wrdoor)
AREAx{x=0-5}Join_0.JoinDMA bit for each DMA channel. It also indicates the remaining space available for writing in the FIFO for the single area selected by the AREAx{x=0-5}Join_0.JoinDMA bit for each DMA channel. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 176: Fifo Access Restrictions
Conditions under which transactions are not performed include the following: ActiveUSB bit is cleared when each endpoint is not joined to FIFO areas and when ForceNAK is not set. There are no restrictions that apply to multiple ports, since individual FIFO areas are independent. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 177: 1.7 Cpuif
For detailed information on ENDIAN modes, refer to “Appendix A: Connection to Little-endian CPU.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 178: Cpuif Mode Setup
The XCS signal is temporarily negated. For example, the same operation is performed as in step Normal register access is possible once this mode setup is complete. Ideally, read the ChipConfig register after setting to check mode setup. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 179 Signals other than those included in Fig. 1-76 in mode setup can be either High or Low, provided the AC ratings are satisfied. The CPUIF mode must always be set after a hard reset, and only while uninitialized period. The following CPUIF descriptions primarily explain Strobe and Big-endian modes. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 180: Block Configuration
– for example, due to carry-over of count values during the access cycle. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 181: Fifo Access (Write)
Use byte-reading if a byte boundary exists. If the FIFO_Rd_0,1 registers are used for word-reading in this case, valid data will only be output on one side. For details, refer to “1.7.3.1.5 FIFO Access Fractional Number Processing.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 182: Fifo Access Fractional Number Processing
Low. If writing to High only from a state in which byte boundaries exist in the FIFO, writing will be ignored (Fig. 1-78 (4)). EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 183 For each access, data is read out in the sequence A, B, C, and D. These are the normal read operations. Before reading After reading Before reading After reading start start start start Fig. 1-79 FIFO reading processing (normal operation) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 184 (4) The join is restored after the 33 bytes of data have been sent from the USB. (1 + 33 bytes) (5) The CPUIF latches the 34-byte ready and starts the continuous operation sequence. (6) 34 bytes of data are word-read. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 185: Ram_Rd Access
1.7.3.1.8 Asynchronous Register Access (Reading) As with synchronous register reading, register data is output to the external bus with the read (asserted for both XCS and XRD) period as the output enable period. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 186: Dma0/Dma1(Dma Ch.0/Ch.1)
If the internal FIFO contains free space for writing or data for reading and counts remain in the DMA_Count_HH,HL,LH,LL registers, XDREQ is asserted and DMA transfer enabled. • Free-run mode If the internal FIFO contains free space for writing or data for reading, XDREQ is asserted and DMA transfer enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 187 Ready < 2 XDREQ Assert Negate Ready (Ready-1 if Transfer quantity ready is odd number) * Req here is the DMA_Config.ReqAssertCount setting, Ready is the FIFO free space and data quantity, and Count is the DMA_Count_HH,HL,LH,LL value. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 188: Terminal Setup
DMA_Stop bit, stop the CPU DMAC (master) first. Fig. 1-81 shows the operational timing for starting transfers in count mode and for stopping transfers using the DMA_Control.DMA_Stop bit before transferring the preset number of counts. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 189 DMA_Ready. (5) XDREQ is negated when the DMA_Count last data is transferred. The DMA circuit is stopped once the DMA_Count quantity has been transferred. Fig. 1-82 Count mode write timing 2 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 190: Count Mode (Read)
DMA_Stop bit, first stop the CPU DMAC (master). Fig. 1-83 shows the operational timing for starting transfers in count mode and the DMA transfer ending once the preset number of counts have been transferred. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 191 (5) XDREQ is asserted when data is written to the FIFO from the USB, permitting data to be read from externally. (6) XDACK is asserted and DMA transfer starts. (7) XDREQ is negated when the DMA_Count last data is transferred. Fig. 1-83 Count mode read timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 192: Free-Run Mode (Write)
DMA_Stop bit, stop the CPU DMAC (master) first. The CPU_IntStat.DMA_Countup bit is set if the DMA_Count_HH,HL,LH,LL register values overflow during DMA transfer in Free-run mode. DMA transfer continues even if this occurs, and DMA_Count_HH,HL,LH,LL also continue and are counted. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 193: Req Assert Count Option (Write)
(3) XDREQ is negated when the continuous transfer quantity (REQ assert count) is complete. (4) Free space for the next continuous transfer (DMA_Ready) exists once the first continuous transfer is complete. DREQ is asserted on receipt of DMA_Ready. Fig. 1-84 REQ assert count option write timing EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 194: Req Assert Count Option (Read)
For detailed information on operational timing, refer to Figures 1-83 and 1-84. 1.7.3.2.9 DMA FIFO Access Fractional Number Processing Refer to “1.7.3.1.5 FIFO Access Fractional Number Processing.” Note that the DMA lacks an opening for byte-reading or writing. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 195: Register Maps
Common registers are shaded on the register maps. Table 2-1 Common register list Port 0 address Port 1 address Register name 0x006 0x206 PortIntStat 0x014, 0x015 0x214, 0x215 WakeupTim_H, WakeupTim_L 0x073 0x273 ClkSelect 0x075 0x275 CPU_Config 0x07E, 0x07F 0x27E, 0x27F CPUIF_MODE EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 196: 2.2 Initial Register Map
0x27E CPUIF_MODE 0xXXXX CPU_Endian BusMode All write accesses to the LSI are treated as write accesses to this register for processing during the uninitialized period. Access to this register is ignored once the initialization period ends. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 197: 2.3 Port 0 Register Maps
Device/Host Common Register Map Registers that can be read from or written to even in the SLEEP state appear in bold italic. All other registers can be read from or written to in the ACTIVE state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 198 2. Register Maps Registers that can be read from or written to even in the SLEEP state appear in bold italic. All other registers can be read from or written to in the ACTIVE state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 199 0x057 RAM_Rd_17 0x00 RAM_Rd_17[7:0] 0x058 RAM_Rd_18 0x00 RAM_Rd_18[7:0] 0x059 RAM_Rd_19 0x00 RAM_Rd_19[7:0] 0x05A RAM_Rd_1A 0x00 RAM_Rd_1A[7:0] 0x05B RAM_Rd_1B 0x00 RAM_Rd_1B[7:0] 0x05C RAM_Rd_1C 0x00 RAM_Rd_1C[7:0] 0x05D RAM_Rd_1D 0x00 RAM_Rd_1D[7:0] 0x05E RAM_Rd_1E 0x00 RAM_Rd_1E[7:0] 0x05F RAM_Rd_1F 0x00 RAM_Rd_1F[7:0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 200 IntMode DREQ_Level DACK_Level CS_Mode CPU_Endian BusMode Initialized 0xXX 0x076 0xXX 0x077 0xXX 0x078 0xXX 0x079 0xXX 0x07A 0xXX 0x07B 0xXX 0x07C 0xXX 0x07D 0x07E CPUIF_MODE 0xXX MergeDMA CPU_Endian BusMode 0xXX BusMode 0x07F CPUIF_MODE MergeDMA CPU_Endian EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 201 0x095 AREA5StartAdrs_L 0x00 StartAdrs[7:2] 0x096 AREA5EndAdrs_H 0x00 EndAdrs[12:8] 0x097 AREA5EndAdrs_L 0x00 EndAdrs[7:2] 0x098 0xXX 0x099 0xXX 0x09A 0xXX 0x09B 0xXX 0x09C 0xXX 0x09D 0xXX 0x09E 0xXX 0x09F AREAnFIFO_Clr 0xXX ClrAREA5 ClrAREA4 ClrAREA3 ClrAREA2 ClrAREA1 ClrAREA0 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 202 JoinEP0CH0 0x0AA AREA5Join_0 0x00 JoinFIFO_Stat JoinDMA JoinCPU_Rd JoinCPU_Wr 0x0AB AREA5Join_1 0x00 JoinEPeCHe JoinEPdCHd JoinEPcCHc JoinEPbCHb JoinEPaCHa JoinEP0CH0 0x0AC 0x0AD 0x0AE ClrAREAnJoin_0 0x00 ClrJoinFIFO_Stat ClrJoinDMA ClrJoinCPU_Rd ClrJoinCPU_Wr 0x0AF ClrAREAnJoin_1 0x00 ClrJoinEPeCHe ClrJoinEPdCHd ClrJoinEPcCHc ClrJoinEPbCHb ClrJoinEPaCHa ClrJoinEP0CH0 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 203: Device Register Map
0x00 EnAlarmEP15IN EnAlarmEP14IN EnAlarmEP13IN EnAlarmEP12IN EnAlarmEP11IN EnAlarmEP10IN EnAlarmEP9IN EnAlarmEP8IN D_AlarmIN_IntEnb_H 0x0CD 0x00 EnAlarmEP7IN EnAlarmEP6IN EnAlarmEP5IN EnAlarmEP4IN EnAlarmEP3IN EnAlarmEP2IN EnAlarmEP1IN D_AlarmIN_IntEnb_L 0x0CE 0x00 EnAlarmEP9OUT EnAlarmEP8OUT EnAlarmEP15OUT EnAlarmEP14OUT EnAlarmEP13OUT EnAlarmEP12OUT EnAlarmEP11OUT EnAlarmEP10OUT D_AlarmOUT_IntEnb_H 0x0CF 0x00 EnAlarmEP7OUT EnAlarmEP6OUT EnAlarmEP5OUT EnAlarmEP4OUT EnAlarmEP3OUT EnAlarmEP2OUT EnAlarmEP1OUT D_AlarmOUT_IntEnb_L EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 204 0x0E7 D_EP0SETUP_7 0x00 SETUP 7[7:0] 0x0E8 D_USB_Address R/(W) 0x00 SetAddress USB_Address [6:0] 0x0E9 0xXX 0x0EA D_SETUP_Control 0x00 ProtectEP0 0x0EB 0xXX 0x0EC 0xXX 0x0ED 0xXX 0x0EE D_FrameNumber_H 0x00 Fn_Invalid FrameNumber [10:8] 0x0EF D_FrameNumber_L 0x80 FrameNumber [7:0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 205 0x00 0x10A D_EPcConfig 0x00 INxOUT IntEP_Mode EndpointNumber[3:0] 0xXX 0x10B 　　　　　　　　　 0x10C D_EPcControl 0x00 AutoForceNAK EnShortPkt DisAF_NAK_Short ToggleStat ToggleSet ToggleClr ForceNAK ForceSTALL 0xXX 0x10D 0xXX 0x10E 0xXX 0x10F EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 206 EnEP15IN_ISO EnEP14IN_ISO EnEP13IN_ISO EnEP12IN_ISO EnEP11IN_ISO EnEP10IN_ISO EnEP9IN_ISO EnEP8IN_ISO 0x12D D_EnEP_IN_ISO_L 0x00 EnEP7IN_ISO EnEP6IN_ISO EnEP5IN_ISO EnEP4IN_ISO EnEP3IN_ISO EnEP2IN_ISO EnEP1IN_ISO 0x12E D_EnEP_OUT_ISO_H R/W 0x00 EnEP9OUT_ISO EnEP8OUT_ISO EnEP15OUT_ISO EnEP14OUT_ISO EnEP13OUT_ISO EnEP12OUT_ISO EnEP11OUT_ISO EnEP10OUT_ISO 0x12F D_EnEP_OUT_ISO_L 0x00 EnEP7OUT_ISO EnEP6OUT_ISO EnEP5OUT_ISO EnEP4OUT_ISO EnEP3OUT_ISO EnEP2OUT_ISO EnEP1OUT_ISO EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 207: Host Register Map
0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x158 H_CHcIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x159 H_CHdIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x15A H_CHeIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x15B 0xXX 0x15C 0xXX 0x15D 0xXX 0x15E 0xXX 0x15F 0xXX EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 208 0x175 H_CH0SETUP_5 0x00 SETUP 5[7:0] 0x176 H_CH0SETUP_6 0x00 SETUP 6[7:0] 0x177 H_CH0SETUP_7 0x00 SETUP 7[7:0] 0x178 0xXX 0x179 0xXX 0x17A 0xXX 0x17B 0xXX 0x17C 0xXX 0x17D 0xXX 0x17E H_FrameNumber_H 0xFF FrameNumber[10:8] 0x17F H_FrameNumber_L 0x07 FrameNumber[7:0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 209 0x198 H_CHaHubAdrs 0x00 HubAdrs[3:0] Port[2:0] 0x199 H_CHaFuncAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] 0x19A H_CHaBO_SupportCtl 0x00 BO_TransportState[1:0] BO_SupportGo 0x19B 0x00 CSW_RcvDataSize[3:0] H_CHaBO_CSW_RcvSize 0x19C 0x00 OUT_Toggle OUT_EP_Number[3:0] H_CHaBO_OUT_EP_Ctl 0x19D H_CHaBO_IN_EP_Ctl 0x00 IN_Toggle IN_EP_Number[3:0] 0x19E H_CHaConditionCode 0x00 ConditonCode[2:0] 0x19F 0xXX EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 210 0x1B7 H_CHcTotalSize_LL 0x00 TotalSize[7:0] 0x1B8 H_CHcHubAdrs 0x00 HubAdrs[3:0] Port[2:0] 0x1B9 H_CHcFuncAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] 0x1BA H_CHcInterval_H 0x00 Interval[10:8] 0x1BB H_CHcInterval_L 0x00 Interval[7:0] 0x1BC H_CHcTranPause 0x00 EnTranPause TranPause 0x1BD 0xXX 0x1BE H_CHcConditionCode 0x00 ConditonCode[2:0] 0x1BF 0xXX EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 211 TotalSize[7:0] 0x1D7 H_CHeTotalSize_LL 0x00 HubAdrs[3:0] Port[2:0] 0x1D8 H_CHeHubAdrs 0x00 0x1D9 H_CHeFuncAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] Interval[10:8] 0x1DA H_CHeInterval_H 0x00 Interval[7:0] 0x1DB H_CHeInterval_L 0x00 0x00 0x1DC H_CHeTranPause EnTranPause TranPause 0xXX 0x1DD ConditonCode[2:0] 0x00 0x1DE H_CHeConditionCode 0xXX 0x1DF EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 212: 2.4 Port 1 Register Maps
Device/Host Common Register Map Registers that can be read from or written to even in the SLEEP state appear in bold italic. All other registers can be read from or written to in the ACTIVE state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 213 2. Register Maps Registers that can be read from or written to even in the SLEEP state appear in bold italic. All other registers can be read from or written to in the ACTIVE state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 214 0x257 RAM_Rd_17 0x00 0x258 RAM_Rd_18 0x00 RAM_Rd_18[7:0] RAM_Rd_19[7:0] 0x259 RAM_Rd_19 0x00 RAM_Rd_1A[7:0] 0x25A RAM_Rd_1A 0x00 RAM_Rd_1B[7:0] 0x25B RAM_Rd_1B 0x00 RAM_Rd_1C[7:0] 0x25C RAM_Rd_1C 0x00 RAM_Rd_1D[7:0] 0x25D RAM_Rd_1D 0x00 RAM_Rd_1E[7:0] 0x25E RAM_Rd_1E 0x00 0x25F RAM_Rd_1F 0x00 RAM_Rd_1F[7:0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 215 IntMode DREQ_Level DACK_Level CS_Mode CPU_Endian BusMode Bus8x16 0xXX 0x276 0xXX 0x277 0xXX 0x278 0xXX 0x279 0xXX 0x27A 0xXX 0x27B 0xXX 0x27C 0xXX 0x27D 0x27E CPUIF_MODE 0xXX MergeDMA CPU_Endian BusMode 0xXX BusMode 0x27F CPUIF_MODE MergeDMA CPU_Endian EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 216 StartAdrs[7:2] 0x295 AREA5StartAdrs_L 0x00 EndAdrs[12:8] 0x296 AREA5EndAdrs_H 0x00 EndAdrs[7:2] 0x297 AREA5EndAdrs_L 0x00 0xXX 0x298 0xXX 0x299 0xXX 0x29A 0xXX 0x29B 0xXX 0x29C 0xXX 0x29D 0xXX 0x29E 0x29F AREAnFIFO_Clr 0xXX ClrAREA5 ClrAREA4 ClrAREA3 ClrAREA2 ClrAREA1 ClrAREA0 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 217 0x2A9 AREA4Join_1 0x00 JoinFIFO_Stat JoinDMA JoinCPU_Rd JoinCPU_Wr 0x2AA AREA5Join_0 0x00 JoinEPeCHe JoinEPdCHd JoinEPcCHc JoinEPbCHb JoinEPaCHa JoinEP0CH0 0x2AB AREA5Join_1 0x2AC 0x2AD 0x00 ClrJoinFIFO_Stat ClrJoinDMA ClrJoinCPU_Rd ClrJoinCPU_Wr 0x2AE ClrAREAnJoin_0 0x00 ClrJoinEPeCHe ClrJoinEPdCHd ClrJoinEPcCHc ClrJoinEPbCHb ClrJoinEPaCHa ClrJoinEP0CH0 0x2AF ClrAREAnJoin_1 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 218: Host Register Map
0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x358 H_CHcIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x359 H_CHdIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0x35A H_CHeIntEnb 0x00 EnTotalSizeCmp EnTranACK EnTranErr EnChangeCondition 0xXX 0x35B 0xXX 0x35C 0xXX 0x35D 0xXX 0x35E 0xXX 0x35F EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 219 0x00 0x375 H_CH0SETUP_5 SETUP 5[7:0] 0x00 0x376 H_CH0SETUP_6 SETUP 6[7:0] 0x00 0x377 H_CH0SETUP_7 SETUP 7[7:0] 0xXX 0x378 0xXX 0x379 0xXX 0x37A 0xXX 0x37B 0xXX 0x37C 0xXX 0x37D 0x37E H_FrameNumber_H 0xFF FrameNumber[10:8] FrameNumber[7:0] 0x37F H_FrameNumber_L 0x07 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 220 HubAdrs[3:0] Port[2:0] 0x398 H_CHaHubAdrs 0x00 0x399 H_CHaFuncAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] BO_TransportState[1:0] 0x00 BO_SupportGo 0x39A H_CHaBO_SupportCtl CSW_RcvDataSize[3:0] 0x00 H_CHaBO_CSW_RcvSize 0x39B OUT_EP_Number[3:0] 0x00 OUT_Toggle 0x39C H_CHaBO_OUT_EP_Ctl 0x00 IN_Toggle IN_EP_Number[3:0] 0x39D H_CHaBO_IN_EP_Ctl ConditonCode[2:0] 0x00 0x39E H_CHaConditionCode 0xXX 0x39F EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 221 TotalSize[7:0] 0x3B7 H_CHcTotalSize_LL 0x00 HubAdrs[3:0] Port[2:0] 0x3B8 H_CHcHubAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] 0x3B9 H_CHcFuncAdrs 0x00 Interval[10:8] 0x3BA H_CHcInterval_H 0x00 Interval[7:0] 0x3BB H_CHcInterval_L 0x00 0x00 0x3BC H_CHcTranPause EnTranPause TranPause 0xXX 0x3BD 0x3BE H_CHcConditionCode 0x00 ConditonCode[2:0] 0xXX 0x3BF EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 222 TotalSize[7:0] 0x3D7 H_CHeTotalSize_LL 0x00 HubAdrs[3:0] Port[2:0] 0x3D8 H_CHeHubAdrs 0x00 0x3D9 H_CHeFuncAdrs 0x00 FuncAdrs[3:0] EP_Number[3:0] Interval[10:8] 0x3DA H_CHeInterval_H 0x00 Interval[7:0] 0x3DB H_CHeInterval_L 0x00 0x00 0x3DC H_CHeTranPause EnTranPause TranPause 0xXX 0x3DD ConditonCode[2:0] 0x00 0x3DE H_CHeConditionCode 0xXX 0x3DF EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 223: Register Details
Addresses are shown as offset addresses from the base address 000h for Port 0 and from the base address 200h for Port 1. Registers and register bits defined for Port 0 but not for Port 1 are indicated accordingly. Port1 Offset Address 0x200 Port0 Offset Address 0x000 Base Address Fig. 3-1 Address notation EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 224: Port0:000H / Port1:200H Mainintstat (Main Interrupt Status)
SLEEP state. Bit5 CPU_IntStat Indirectly specifies interrupt factors. It is set to “1” when the CPU_IntStat register includes interrupt factors and the CPU_IntEnb register bit corresponding to the interrupt factors is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 225 Bit0 FinishedPM Directly specifies interrupt factors. It is set to “1” on reaching the particular specified state when GoSLEEP or GoACTIVE is set by the PM_Control register. This bit is enabled even in SLEEP state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 226: Port0:001H / Port1:N/A Usb_Deviceintstat (Usb Device Interrupt Status)
This bit allows reading even in SLEEP state. Bit4 D_BulkIntStat Indirectly specifies interrupt factors. Set to “1” when D_BulkIntStat register includes interrupt factors and the D_BulkIntEnb register bit corresponding to the interrupt factors is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 227 Bit0 D_EPrIntStat Indirectly specifies interrupt factors. Set to “1” when the D_EPrIntStat register includes interrupt factors and the D_EPrIntEnb register bit corresponding to the interrupt factors is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 228: Port0:002H / Port1:202H Usb_Hostintstat (Usb Host Interrupt Status)
USB host function is enabled in SUSPEND state. Bit5 H_SIE_IntStat1 Indirectly specifies interrupt factors. Set to “1” when the H_SIE_IntStat1 register includes interrupt factors and the H_SIE_IntEnb1 register bit corresponding to the interrupt factors is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 229 Bit0 H_CHrIntStat Indirectly specifies interrupt factors. Set to “1” when the H_CHrIntStat register includes interrupt factors and the H_CHrIntEnb register bit corresponding to the interrupt factors is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 230: Port0:003H / Port1:203H Cpu_Intstat (Cpu Interrupt Status)
The DMA_Count_HH,HL,LH,LL values return to 0, and DMA operation continues. Bit0 DMA_Cmp Directly specifies interrupt factors. Set to “1” when the DMA transfer is stopped or if the specified transfer quantity has been sent and end processing is complete. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 231: Port0:004H / Port1:204H Fifo_Intstat (Fifo Interrupt Status)
Set to “1” if the FIFO area for the corresponding area becomes full when the AREAn{n=0-5}Join_0.JoinFIFO_Stat bit is set to “1.” Bit0 FIFO_Empty Directly specifies interrupt factors. Set to “1” if the FIFO area for the corresponding area becomes empty when the AREAn{n=0-5}Join_0.JoinFIFO_Stat bit is set to “1.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 232: Port0:006H / Port1:206H Rootintstat (Root Interrupt Status)
It indicates the port generating the interrupt when the XINT terminal is asserted. Bit7-2 Reserved Bit1 Port1MainIntStat Indirectly specifies interrupt factors. Indicates that Port 1 is the interrupt source. Bit0 Port0MainIntStat Indirectly specifies interrupt factors. Indicates that Port 0 is the interrupt source. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 233: Port0:008H / Port1:208H Mainintenb (Main Interrupt Enable)
This register permits or prohibits interrupt signal (XINT) assertion by MainIntStat register interrupt factors. Interrupts are permitted if the corresponding bit is set to “1.” The EnUSB_DeviceIntStat, EnUSB_HostIntStat, and EnFinishedPM bits are enabled even in SLEEP state. The EnUSB_DeviceIntStat bit is not defined for Port 1. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 234: Port0:009H / Port1:N/A Usb_Deviceintenb (Device Interrupt Enable)
0: Disable 1: Enable This register is not defined for Port 1. Permits or prohibits MainIntStat register USB_DeviceIntStat bit assertion by USB_DeviceIntStat register interrupt factors. The EnVBUS_Changed and EnD_SIE_IntStat bits are enabled even in SLEEP state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 235: Port0:00Ah / Port1:20Ah Usb_Hostintenb (Host Interrupt Enable)
0: Disable 1: Enable 0: EnH_CHrIntStat 0: Disable 1: Enable Permits or prohibits MainIntStat register USB_HostIntStat bit assertion by USB_HostIntStat register interrupt factors. The EnVBUS_Err bit and EnLineStateChanged bit are enabled even in SLEEP state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 236: Port0:00Bh / Port1:20Bh Cpu_Intenb (Cpu Interrupt Enable)
00Bh CPU_IntEnb 7: EnRAM_RdCmp 0: Disable 1: Enable / Host 1: EnDMA_CountUp 0: Disable 1: Enable 0: EnDMA_Cmp 0: Disable 1: Enable Permits or prohibits MainIntStat register CPU_IntStat bit assertion by CPU_IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 237: Port0:00Ch / Port1:20Ch Fifo_Intenb (Fifo Interrupt Enable)
1: Enable / Host 2: EnFIFO_NotEmpty 0: Disable 1: Enable 1: EnFIFO_Full 0: Disable 1: Enable 0: EnFIFO_Empty 0: Disable 1: Enable Permits or prohibits MainIntStat register FIFO_IntStat bit assertion by FIFO_IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 238: Port0:010H / Port1:210H Revisionnum (Revision Number)
3: RevisionNum [3] 2: RevisionNum [2] 1: RevisionNum [1] 0: RevisionNum [0] Indicates the LSI revision number. This register can be accessed even in SLEEP state. The revision number for the current specifications is 0x08. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 239: Port0:011H / Port1:211H Chipreset (Chip Reset)
Note that this register should only be written to for resets. Writing to this register in contravention of the AC spec except for resets will cause malfunctions. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 240: Port0:012H / Port1:212H Pm_Control (Power Management Control)
XCS and CA9 terminal as the CPU writing state ends. This minimizes unnecessary power consumption, since the CPU interface initial driver is off if an attempt is made to operate signal lines other than the XCS and CA9 terminal. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 241 PM_State will be 0b01 if the referenced port is in SLEEP state and the other ports are in ACTIVE state. This bit should not be referenced, since it varies in sequence to the corresponding state from when the GoSLEEP or GoACTIVE bits are set until when MainIntStat.FinishedPM interrupt status is set. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 242: Port0:014H-015H / Port1:214H-215H Wakeuptim_H,L (Wakeup Time High, Low)
The internal SCLK must be stabilized to 60 MHz ±10% within 5.1 ms after USB RESET detection if dropping to SLEEP state for USB SUSPEND during device operation. The total time for oscillator stabilization time + PLL stabilization time (within 250 µs) must therefore not exceed 5.1 ms. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 243: Port0:016H / Port1:216H H_Usb_Control (Host Usb Control )
7: VBUS_Enb 0: Disable 1: Enable / Host This sets host-related operations. This register is enabled even in SLEEP state. Bit7 VBUS_Enb Sets the VBUSEN terminal (output) state. The default is Low level. Bit6-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 244: Port0:017H / Port1:217H H_Xcvrcontrol (Host Xcvr Control)
Selects and enables the HS, FS, or LS transceiver. 00: High Speed transceiver 01: Full Speed transceiver 10: Reserved 11: Low Speed transceiver This bit should not be set manually. It is automatically set by the hardware when H_NogoControl_0.AutoMode is set. Bit3-2 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 245 However, to detect signal line change status, refer to “1.2.2.2 Signal Line Change Status Usage” when this bit needs setting. OpMode “Normal Operation” Normal usage state “2Non-Driving” Non-used state “Disable Bitstuffing and NRZI encoding” Bitstuffing and NRZI encoding functions disabled in normal usage state “Power-Down” Only single-end receiver used EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 246: Port0:018H / Port1:N/A D_Usb_Status (Device Usb Status)
The HS receiver received value is indicated if XcvrSelect is “0” (with HS transceiver selected). The USB bus activity is indicated when TermSelect is “0.” LineState TermSelect DP / DM LineState [1:0] Don’t Care Bus activity 0b00 0b01 0b10 0b11 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 247: Port0:019H / Port1:219H H_Usb_Status (Host Usb Status)
Activity present: 0b01 No activity: 0b00 01 or 11 0b00 01 or 11 0b01 01 or 11 0b10 01 or 11 0b11 Note: The XcvrSelect[1:0] = “10” code is reserved and does not guarantee the operation. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 248: Port0:01Bh / Port1 Mtm_Config (Multi Transceiver Macro Config)
Sets HS transmitter slew rate to one of four levels. 00: Slow 01: ↑ 10: ↓ 11: Fast Bit3-2 Reserved Bit1-0 MTM_TermValue[1:0] Sets HS transmission route termination to one of four levels. 00: High 01: ↑ 10: ↓ 11: Low EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 249: Port0:01Fh / Port1:21Fh Hostdevicesel (Host Device Select)
USB host block is suspended. If HOST x DEVICE is “1,” i.e., in host mode, the system clock is fed to the common block and USB host block, and provision of the system clock to the USB device block is suspended. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 250: Port0:020H / Port1:220H Fifo_Rd_0 (Fifo Read 0)
If this register is read when the FIFO contains byte boundaries, valid data is output to one side only. For detailed information, refer to “FIFO Access Fractional Number Processing.” To read out FIFO data using this register, the quantity of data that can be read should first be checked using the FIFO_RdRemain_H,L registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 251: Port0:022H / Port1:222H Fifo_Wr_0(Fifo Write 0)
For detailed information, refer to “FIFO Access Fractional Number Processing.” To write data to the FIFO using this register, the quantity of data that can be written must first be checked using the FIFO_WrRemain_H,L registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 252 Indicates the quantity of readable data within the FIFO connected to the CPU I/F by the AREAn{n=0-5}Join_0.JoinCPU_Rd bit. The FIFO_RdRemain_H and FIFO_RdRemain_L registers must both be accessed as a pair to obtain the FIFO readable data quantity. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 253 FIFO. Allow at least one CPU cycle before checking the FIFO free space. The FIFO_WrRemain_H and FIFO_WrRemain_L registers must be accessed as a pair to obtain FIFO free capacity. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 254 Enables reading of data in byte units from the FIFO set by the AREAn{n=0-5}Join_0.JoinCPU_Rd bit. To read out FIFO data using this register, the quantity of data that can be read must first be checked using the FIFO_RdRemain_H,L registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 255 Enables writing of data in byte units to the FIFO set by the AREAn{n=0-5}Join_0.JoinCPU_Wr bit. To write data to the FIFO using this register, the quantity of data that can be written must first be checked using the FIFO_WrRemain_H,L registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 256 RAM_RdControl register bit has been set and the RAM_Rd function started. Values cannot be guaranteed if this register is read while the RAM_Rd function is operating. Also note that writing to this register while the RAM_Rd function is operating will result in malfunctions. Bit1-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 257 1F} register value is enabled, the CPU_IntStat.RAM_RdCmp bit is set to “1,” and the bit is automatically cleared. The function for the RAM_GoRdCBW_CSW bit takes priority if set concurrently with the RAM_GoRdCBW_CSW bit. Bit5-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 258 RAM_Rd function is operating will result in malfunctions. Note that this register can be set to a maximum of 32 bytes. Setting a data quantity exceeding 32 bytes will result in malfunctions. Bit1-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 259 RAM_WrDoor_0,1 registers. Note that RAM_WrAdrs cannot be accurately checked immediately after writing to the RAM_WrDoor_0,1 registers. Allow at least one CPU cycle before checking RAM_WrAdrs. For detailed information on writing data, refer to “RAM_WrDoor_0,1 Registers.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 260 Note, however, that if the area to which descriptor data is written overlaps an area retained by another endpoint, the data can be overwritten. For a USB host, data can be written to the CBW areas by the RAM_WrDoor_0,1 registers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 261: Port0:058H / Port1:258H Ram_Rd_18 (Ram Read 18)
Port0:05Bh / Port1:25Bh RAM_Rd_1B (RAM Read 1B) 3.1.64 Port0:05Ch / Port1:25Ch RAM_Rd_1C (RAM Read 1C) 3.1.65 Port0:05Dh / Port1:25Dh RAM_Rd_1D (RAM Read 1D) 3.1.66 Port0:05Eh / Port1:25Eh RAM_Rd_1E (RAM Read 1E) 3.1.67 Port0:05Fh / Port1:25Fh RAM_Rd_1F (RAM Read 1F) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 262 If the value set in the RAM_RdCount register is less than 32 bytes, the data read from RAM is stored in sequence from RAM_Rd_00. Register values above the count set in the RAM_RdCount register (e.g., RAM_Rd_10 to RAM_Rd_1F when the count setting is “16”) become invalid. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 263: Port0:061H / Port1:261H Dma_Config (Dma Config)
XDREQ is first negated, then asserted again once the free space or data is confirmed as being at least as equal to the assert count. In other words, transfers for the assert count number set are guaranteed for a single XDREQ assert. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 264 Negate Transferable quantity Mode ReqAssertCount [1:0] 16bit mode 8bit mode 0b00 Normal Normal 0b01 16Byte(8Count) 16Byte(16Count) 0b10 32Byte(16Count) 32Byte(32Count) 0b11 64Byte(32Count) 64Byte(64Count) The REQ assert count option is not used for the 00 (Normal) setting. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 265: Port0:062H / Port1:262H Dma_Control (Dma Control)
“0.” The CPU_IntStat register DMA_Cmp bit is also set to “1.” To restart the DMA transfer, check the DMA_Running bit or DMA_Cmp bit, then wait for the DMA to end. Bit0 DMA_Go Setting this bit to “1” starts the DMA transfer. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 266: (Dma Fifo Remain High, Low)
For writing, this indicates the quantity of free space in the FIFO connected to the DMA by the AREAn{n=0-5}Join_0.JoinDMA bit. The correct FIFO free space cannot be checked using this register immediately after a DMA write. Allow at least one CPU cycle before checking the FIFO free space. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 267: (Dma Transfer Byte Counter High/High, High/Low)
9: DMA_Count [9] 8: DMA_Count [8] DMA Transfer Byte Counter Low 0000h 7: DMA_Count [7] 6: DMA_Count [6] 5: DMA_Count [5] 4: DMA_Count [4] 3: DMA_Count [3] 2: DMA_Count [2] 1: DMA_Count [1] 0: DMA_Count [0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 268 The count cannot be accurately checked using these registers immediately after DMA writing. Allow at least one CPU cycle before checking the count. These registers should be read out in the sequence of DMA_Count_HH,HL followed by DMA_Count_LH,LL. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 269: Port0:06Ch / Port1:26Ch Dma_Rddata_0 (Dma Read Data 0)
FIFO connected to the DMA by the AREAn{n=0-5}Join_0.JoinDMA bit. Here, the DMA_Control.Dir bit must be set to DMA read. DMA access is possible in the same way, whether DMA_RdData_0 or DMA_RdData_1 is accessed, when operating in 8-bit mode. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 270: Port0:06Eh / Port1:26Eh Dma_Wrdata_0 (Dma Write Data 0)
FIFO connected to the DMA by the AREAn{n=0-5}Join_0.JoinDMA bit. The DMA_Control.Dir bit must be set to DMA write here. DMA access is possible in the same way, whether DMA_WrData_H or DMA_WrData_L is accessed when operating in 8-bit mode. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 271: Port0:071H / Port1:271H Modeprotect (Mode Protection)
For normal use, to protect the CPU_Config and ClkSelect register settings, the CPU_Config and ClkSelect registers should be set as required before setting this register to a value other than 56h (e.g. 00h). This bit can be accessed even in SLEEP state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 272: Port0:073H / Port1:273H Clkselect (Clock Select)
This register must be set before operating the LSI. The register is enabled even in SLEEP state. Bit7-1 Reserved Bit1-0 ClkSelect This sets the clock frequency used by the LSI. 0: 12 MHz 1: 24 MHz EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 273: Cpu_Config (Cpu Configuration)
This sets the XINT output mode. 0: 1/0 mode 1: Hi-z/0 mode Bit5 DREQ_Level This sets the XDREQ logic level. 0: Negative logic 1: Positive logic Bit4 DACK_Level This sets the XDACK logic level. 0: Negative logic 1: Positive logic EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 274 0: 16bit Strobe mode 1: 16bit BE mode This bit indicates the value written to the CPUIF_MODE register during the initialization period. Bit0 Initialized This flag indicates that initialization is complete. It is normally read as “1.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 275: Port0:07E-07Fh / Port1:27Eh-27Fh Cpuif_Mode (Cpuif Mode)
The DMA for this chip should be controlled exclusively by the software to prevent simultaneously launching with Port 0 and Port 1. Bit10,2 CPU_Endian Sets the CPUIF endian. Bit9,1 BusMode Sets the CPUIF write access mode. Bit14-11,9,6-3,0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 276: (Area 0 Start Address High, Low)
The area assigned to the FIFO area AREAx{x=0-5} extends up to the first byte of the address set by AREAx{x=0-5}EndAdrs. The AREAnFIFO_Clr register ClrAREAx{x=0-5} bit must always be set to “1” and the FIFO area AREAx{x=0-5} FIFO cleared after setting AREAx{x=0-5}StartAdrs and AREAx{x=0-5}EndAdrs. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 277 Note that the LSI will not operate correctly if the MaxSize for the USB device/host joined exceeds the area set here. The same applies if the FIFO area overlaps another FIFO area. This LSI has 4.5 kB of internal RAM and supports addresses up to 0x1200. Bit1-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 278: (Area 0 End Address High, Low)
The area assigned to the FIFO area AREAx{x=0-5} extends up to the first byte of the address set by AREAx{x=0-5}EndAdrs. The AREAnFIFO_Clr register ClrAREAx{x=0-5} bit must always be set to “1” and the FIFO area AREAx{x=0-5} FIFO cleared after setting AREAx{x=0-5}StartAdrs and AREAx{x=0-5}EndAdrs. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 279 Note that the LSI will not operate correctly if the MaxSize for the USB device/host joined exceeds the area set here. The same applies if the FIFO area overlaps another FIFO area. This LSI has 4.5 kB of internal RAM and supports addresses up to 0x1200. Bit1-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 280: Port0:09Fh / Port1:29Fh Areanfifo_Clr (Area N Fifo Clear )
DMA is running (i.e., while the DMA_Running bit is “1”). This register only initializes the data retention information. It does not write or clear the data itself. Data in the RAM therefore cannot be cleared by this bit. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 281: Port0:0A0H / Port1:2A0H Area0Join_0 (Area 0 Join 0)
FIFO_Rd_0,1, FIFO_ByteRd, and FIFO_Wr_0,1 registers. Only one of the JoinDMA, JoinCPU_Rd, and JoinCPU_Wr bits should be set to “1” at any given time. Writing “1” to more than one bit simultaneously may destabilize operations. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 282: Port0:0A1H / Port1:2A1H Area0Join_1 (Area 0 Join 1)
EPb or channel EPb. Bit1 JoinEPaCHa This connects endpoint EPa or channel CHa to the FIFO area AREAx{x=0-5}. Connecting enables performance of the transactions related to data transfers using endpoint EPa or channel EPa. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 283 Exercise caution when setting multiple JoinEPxCHx{x=0,a-e} bits simultaneously to the same FIFO area. Unforeseen operations may result, depending on the transaction order. We recommend against setting JoinEPxCHx{x=0,a-e}bits to the same FIFO area under normal conditions. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 284: Port0:0Aeh / Port1:2Aeh Clrareanjoin_0 (Clear Area N Join 0)
Do not set this register bit to “1” while the FIFO area is connected to the port (the bit corresponding to the AREAn{n=0-5}Join_0 register is set to “1”) and each port is running. Doing so will lead to malfunctions. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 285: Port0:0Afh / Port1:2Afh Clrareanjoin_1 (Clear Area N Join 1)
Do not set this register bit to “1” while the FIFO area is connected to the endpoint or channel (the bit corresponding to the AREAn{n=0-5}Join_1 register is set to “1”) and each endpoint and channel transaction is executed. Doing so will lead to malfunctions. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 286: 3.2 Device Register Details
Addresses are shown as offset addresses from the base address 000h for Port 0. Port1 Offset Address 0x200 Port0 Offset Address 0x000 Base Address Fig. 3-1 Address notation EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 287: Port0:0B0H / Port1:N/A D_Sie_Intstat (Device Sie Interrupt Status)
DisBusDetect bit to “1” to disable USB RESET/SUSPEND state detection to prevent incorrect detection of continuous resets. The DisBusDetect bit should be cleared to “0” to enable USB RESET/SUSPEND state detection after the reset processing has ended. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 288 The firmware should perform the following processing to prevent assertion of the XINT interrupt signal by the interrupt status when switching from this state. <When changing from DEVICE mode in ACTIVE state> Process and clear the interrupt status (D_SIE_IntStat.Bit5 to 0) Disable the interrupt status (D_SIE_IntEnb.Bit5 to 0) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 289 3. Register Details <When changing to DEVICE mode in ACTIVE state> Clear the interrupt status (D_SIE_IntStat.Bit5 to 0) Enable the interrupt status (D_SIE_IntEnb.Bit5 to 0) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 290: Port0:0B3H / Port1:N/A D_Bulkintstat (Device Bulk Interrupt Status)
This is set to “1” when the 13 CSW bytes are sent correctly. Bit2 CSW_Err Directly specifies interrupt factors. This is set to “1” when an error (ACK is not returned) occurs during CSW transmission. Bit1-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 291: Port0:0B4H / Port1:N/A D_Eprintstat (Device Epr Interrupt Status)
Bit2 D_EPcIntStat Indirectly specifies interrupt factors. This is set to “1” when the D_EPcIntStat register contains an interrupt factor and the D_EPcIntEnb register bit corresponding to the interrupt factor is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 292 Bit0 D_EPaIntStat Indirectly specifies interrupt factors. This is set to “1” when the D_EPaIntStat register contains an interrupt factor and the D_EPaIntEnb register bit corresponding to the interrupt factor is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 293: Port0:0B5H / Port1:N/A D_Ep0Intstat (Device Ep0 Interrupt Status)
This is set to “1” when a NAK is returned in an IN transaction. Bit2 OUT_TranNAK Directly specifies interrupt factors. This is set to “1” when a NAK is returned in response to an OUT or PING transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 294 This is set to “1” if a STALL is returned in an IN transaction, if a packet error occurs, or if the handshake times out. Bit0 OUT_TranErr Directly specifies interrupt factors. This is set to “1” if a STALL is returned in an OUT transaction or if a packet error occurs. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 295: Port0:0B6H / Port1:N/A D_Epaintstat (Device Epa Interrupt Status)
This is set to “1” when a NAK is returned in an IN transaction. Bit2 OUT_TranNAK Directly specifies interrupt factors. This is set to “1” when a NAK is returned in response to an OUT or PING transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 296 This is set to “1” if a STALL is returned in an IN transaction, if a packet error occurs, or if the handshake times out. Bit0 OUT_TranErr Directly specifies interrupt factors. This is set to “1” if a STALL is returned in an OUT transaction or if a packet error occurs. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 297: Port0:0Bch-0Bdh / Port1:N/A D_Alarmin_Intstat_H,L
“1.” A NAK is returned to the host for endpoints cleared to “0.” Enable transactions by joining the endpoint to the FIFO area by setting the D_EPx{x=0,a-e} registers appropriately and using the AREAn{n=0-5}Join.JoinEPxCHx{x=0,a-e} bit if the corresponding bit of this register is set. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 298: Port0:0Beh-0Bfh / Port1:N/A D_Alarmout_Intstat_H,L
PING token is issued by the host. Enable transactions by joining the endpoint to the FIFO area by setting the D_EPx{x=0,a-e} registers appropriately and using the AREAn{n=0-5}Join.JoinEPxCHx{x=0,a-e} bit if the corresponding bit of this register is set. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 299: Port0:0C0H / Port1:N/A D_Sie_Intenb (Device Sie Interrupt Enable)
0: Disable 1: Enable 0: EnSetAddressCmp 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register D_SIE_IntStat bit using the D_SIE_IntStat register interrupt factors. The EnNonJ bit is enabled even in SLEEP state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 300: Port0:0C3H / Port1:N/A D_Bulkintenb (Device Bulk Interrupt Enable)
5: EnCBW_Err 0: Disable 1: Enable 3: EnCSW_Cmp 0: Disable 1: Enable 2: EnCSW_Err 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register D_BulkIntStat bit using the D_BulkIntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 301: Port0:0C4H / Port1:N/A D_Eprintenb (Device Epr Interrupt Enable)
2: EnD_EPcIntStat 0: Disable 1: Enable 1: EnD_EPbIntStat 0: Disable 1: Enable 0: EnD_EPaIntStat 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register D_EPrIntStat bit using the D_EPrIntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 302: Port0:0C5H / Port1:N/A D_Ep0Intenb (Device Ep0 Interrupt Enable)
2: EnOUT_TranNAK 0: Disable 1: Enable 1: EnIN_TranErr 0: Disable 1: Enable 0: EnOUT_TranErr 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register D_EP0IntStat bit using the D_EP0IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 303: Port0:0C6H / Port1:N/A D_Epaintenb (Device Epa Interrupt Enable)
2: EnOUT_TranNAK 0: Disable 1: Enable 1: EnIN_TranErr 0: Disable 1: Enable 0: EnOUT_TranErr 0: Disable 1: Enable These permit or prohibit assertion of the D_EPrIntStat register EPx{x=a-e}IntStat bit using the D_EPx{x=a-e}IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 304: Port0:0Cch-0Cdh / Port1:N/A D_Alarmin_Intenb_H,L
3: EnAlarmEP3IN 0: Disable 1: Enable 2: EnAlarmEP2IN 0: Disable 1: Enable 1: EnAlarmEP1IN 0: Disable 1: Enable This permits or prohibits assertion of the D_EPrIntStat register AlarmIN_IntStat bit using the D_AlarmIN_IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 305: Port0:0Ceh-0Cfh / Port1:N/A D_Alarmout_Intenb_H,L
3: EnAlarmEP3OUT 0: Disable 1: Enable 2: EnAlarmEP2OUT 0: Disable 1: Enable 1: EnAlarmEP1OUT 0: Disable 1: Enable This permits or prohibits assertion of the D_EPrIntStat register AlarmOUT_IntStat bit using the D_AlarmOUT_IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 306: Port0:0D0H / Port1:N/A D_Negocontrol (Device Negotiation Control)
This is automatically set to “1” to enable the NonJ state detection function upon detection of the USB SUSPEND state when using the AutoNegotiation function. Clear this bit to “0” to reset from the USB SUSPEND state. For detailed information on the AutoNegotiation function, refer to the “Functions: AutoNegotiation Function” description. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 307 Bit0 ActiveUSB The LSI stops all USB device functions, since this bit is cleared to “0” after a hard reset. Setting this bit to “1” after setting the LSI allows operation as a USB device. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 308: Port0:0D3H / Port1:N/A D_Xcvrcontrol (Device Xcvr Control)
“Disable Bitstuffing and NRZI encoding” Set to this state when in USB test mode. “Power-Down” Set to this state when in USB SUSPEND state. * We recommend setting this register to “41h” when the USB cable has been disconnected. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 309: Port0:0D4H / Port1:N/A D_Usb_Test (Device Usb_Test)
XcvrControl register TermSelect and XcvrSelect bits should be set according to speed, and OpMode should be set to “10” (Disable Bitstuffing and NRZI encoding) before setting the EnHS_Test bit to “1” in this test mode. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 310 PID and CRC are added by SIE when sending test packets. This means that the data written to the FIFO consists of data from the following DATA0 PID data to the CRC16 data of the test packet data described in the USB standard Rev 2.0. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 311: Port0:0D6H / Port1:N/A D_Epncontrol (Device Endpoint Control)
This write-only register sets endpoint operations. Bit7 AllForceNAK This sets the ForceNAK bit to “1” for all endpoints. Bit6 EPrForceSTALL This sets the ForceSTALL bit to “1” for the EPa, EPb, EPc, EPd, and EPe endpoints. Bit5-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 312: Port0:0D8H / Port1:N/A D_Bulkonlycontrol (Device Bulkonly Control)
CBW support, refer to the BulkOnlyConfig register section. Bit1 GoCSW_Mode Setting this bit to “1” runs CSW support for the corresponding endpoint. For detailed information on the endpoint running CSW support, refer to the BulkOnlyConfig register section. Bit0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 313: Port0:0D9H / Port1:N/A D_Bulkonlyconfig (Device Bulkonly Configuration)
BulkOnlyControl.GoCSW_Mode bit when endpoint EPc is the IN endpoint. Do not enable the bulk-only support function with more than one OUT endpoint. Similarly, do not enable the bulk-only support function with more than one IN endpoint. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 314 BulkOnlyControl.GoCBW_Mode bit when endpoint EPa is the OUT endpoint. Similarly, CSW support is implemented by setting the BulkOnlyControl.GoCSW_Mode bit when endpoint EPa is the IN endpoint. Do not enable the bulk-only support function with more than one OUT endpoint. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 315: Port0:0E0H / Port1:N/A D_Ep0Setup_0 (Device Ep0 Setup 0)
Set with the higher 8 bits of Wvalue. EP0SETUP_4 Set with the lower 8 bits of WIndex. EP0SETUP_5 Set with the higher 8 bits of WIndex. EP0SETUP_6 Set with the lower 8 bits of WLength. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 316 3. Register Details EP0SETUP_7 Set with the higher 8 bits of WLength. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 317: Port0:0E8H / Port1:N/A D_Usb_Address (Device Usb Address)
SetAddress() request is complete and USB_Address has been set. Bit7 Reserved Bit6-0 USB_Address This sets the USB address. This is written to automatically by the AutoSetAddress function. Writing is possible, but it will be rewritten automatically on receiving a SetAddress() request. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 318: Port0:0Eah / Port1:N/A D_Setup_Control(Device Setup Control)
“0,” the ForceNAK bits are set to “1,” and the ToggleStat bits are set to “1.” Since the ProtectEP0 bit is set when the SETUP transaction is run, it is also set for a SetAddress() request. Setting this bit to “1” prevents changes to EP0 ForceNAK and ForceSTALL bit settings. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 319: Port0:0Eeh-0Efh / Port1:N/A D_Framenumber_H,L
This indicates the USB frame number updated each time an SOF token is received. Bit15 FnInvalid This bit is set to “1” if an error occurs in the SOF packet received. Bit14-11 Reserved Bit10-0 FrameNumber[10:0] This indicates FrameNumber for the SOF packet received. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 320: Port0:0F0H / Port1:N/A D_Ep0Maxsize (Device Ep0 Max Packet Size)
This sets the endpoint EP0. Bit7 Reserved Bit6-3 EP0MaxSize[6:3] This sets MaxPacketSize for endpoint EP0. This endpoint can be used with any of the sizes shown below selected. 8, 16, 32, or 64 bytes 64 bytes Bit2-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 321: Port0:0F1H / Port1:N/A D_Ep0Control (Device Ep0 Control)
The D_DescAdrs_H,L registers are incremented by the amount of data transmitted for each transaction, and the D_DescSize_H,L registers are decremented by the amount of data transmitted. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 322 ReplyDescriptor bit is cleared to “0,” and the D_EP0IntStat register DescriptorCmp bit and D_EP0IntStat register IN_TranACK bit are set to “1.” For further details, refer to the section that describes how functions are used. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 323: Port0:0F2H / Port1:N/A D_Ep0Controlin (Device Ep0 Control In)
ToggleClr bit, the ToggleClr bit function is given precedence. Bit2 ToggleClr This clears the endpoint EP0 IN transaction toggle sequence bit to “0.” If set at the same time as the ToggleSet bit, this bit function is given precedence. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 324 “0” and cannot be set to “1” while the D_SETUP_Control.ProtectEP0 bit is “1.” If a transaction is underway, this bit setting will be enabled from the subsequent transaction for a preset duration after the start of the transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 325: Port0:0F3H / Port1:N/A D_Ep0Controlout (Device Ep0 Control Out)
If the transaction is already running when this bit is set to “1,” the bit is not set until the transaction ends. It is set to “1” once the transaction ends. The bit is set to “1” immediately if the transaction is not underway. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 326 “0” and cannot be set to “1” while the D_SETUP_Control.ProtectEP0 bit is “1.” If a transaction is underway, this bit setting will be enabled from the subsequent transaction for a preset duration after the start of the transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 327: Port0:0F8H-0F9H / Port1:N/A D_Epamaxsize_H,L
8, 16, 32, or 64 bytes 512 bytes The transfer quantity can be set as required within the ranges shown below when using the endpoint for interrupt transfers. Up to 64 bytes Up to 1,024 bytes EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 328 3. Register Details The transfer quantity can be set as required within the ranges shown below when using the endpoint for isochronous transfers. 1 to 1,023 bytes 1 to 1,024 bytes EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 329: Port0:0Fah / Port1:N/A D_Epaconfig (Device Epa Configuration)
Whether or not PING flow control is used for this endpoint is set for the OUT direction (INxOUT = 0). Set this bit to “1” for the Interrupt OUT endpoint. − Set for Bulk OUT endpoint. Bulk OUT − Set for Interrupt OUT endpoint. Interrupt OUT EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 330 3. Register Details Bit5 Set to “1” for Isochronous transfer. Set to “0” for endpoints using bulk transfer or interrupt transfer. Bit4 Reserved Bit3-0 EndpointNumber This sets an endpoint number between 0x1 and 0xF. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 331: Port0:0Fch / Port1:N/A D_Epacontrol (Device Epa Control)
* This automatically sets the ForceNAK bit to “1” if a short packet is received at the end of a normal OUT transaction. The default setting is AF_NAK_Short function enabled. Setting this bit to “1” disables the AF_NAK_Short function. If the AutoForceNAK bit is set to “1,” the AutoForceNAK bit takes precedence. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 332 Setting this bit to “1” returns a STALL response to the endpoint EPx{x=a-e} transaction. This bit takes precedence over the ForceNAK bit setting. If a transaction is underway, this bit setting will be enabled from the subsequent transaction for a preset duration after the start of the transaction. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 333: Port0:120H-121H / Port1:N/A D_Descadrs_H,L
FIFO for other endpoints using D_DescAdrs_H,L and D_DescSize_H,L register specifications. Ideally, this should be from the address (0x0030) after the CSW area has been reserved to the first address of the area reserved in AREA0 to 5. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 334: Port0:122H-123H / Port1:N/A D_Descsize_H,L (Device Descriptor Size High, Low)
FIFO for other endpoints using D_DescAdrs_H,L and D_DescSize_H,L register specifications. Ideally, this should be from the address (0x0030) after the CSW area has been reserved to the first address of the area reserved in AREA0 to 5. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 335: Port0:126H / Port1:N/A D_Ep_Dma_Ctrl (Device Ep Dma Control)
This sets the corresponding endpoint EnShortPkt bit to “1” if the amount of data remaining in the FIFO is less than the maximum packet size after DMA ends. It is enabled when the endpoint connected to DMA is in the IN direction. Bit5-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 336: Port0:128H-129H / Port1:N/A D_Enep_In_H,L
The response returned to the IN token depends on the D_EnEP_IN_ISO_H,L setting. A zero-length packet is returned to the host for an endpoint for which the corresponding bit is set to “1.” A NAK is returned to the host for an endpoint cleared to “0.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 337: Port0:12Ah-12Bh / Port1:N/A D_Enep_Out_H,L
PING token is issued by the host. If the corresponding bit in this register is set, enable transactions by appropriately setting the D_EPx{x=0,a-e} related registers and joining the endpoint to the FIFO area using the AREAn{n=0-5}Join.JoinEPxCHx{x=0,a-e} bit. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 338: Port0:12Ch-12Dh / Port1:N/A D_Enep_In_Iso_H,L
The response returned to the IN token depends on the D_EnEP_IN_ISO_H,L setting. A zero-length packet is returned to the host for an endpoint for which the corresponding bit is set to “1.” A NAK is returned to the host for an endpoint cleared to “0.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 339: (Device Enable Endpoint-Out Isochronous High, Low)
PING token is issued by the host. If the corresponding bit in this register is set, enable transactions by appropriately setting the D_EPx{x=0,a-e} related registers and joining the endpoint to the FIFO area using the AREAn{n=0-5}Join.JoinEPxCHx{x=0,a-e} bit. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 340: 3.3 Host Register Details
Addresses are shown as offset addresses from the base address 000h for Port 0 and from the base address 200h for Port 1. Port1 Offset Address 0x200 Port0 Offset Address 0x000 Base Address Fig. 3-2 Address notation EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 341: Port0:140H / Port1:340H H_Sie_Intstat_0 (Host Sie Interrupt Status 0)
“1”, and subsequent processing corresponds to HS devices. This bit must therefore always be cleared to “0” when the device is disconnected. Bit0 DetectDevChirpNG Directly specifies interrupt factors. Set to “1” if an error chirp signal is received from the device. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 342 Process and clear the interrupt status (H_SIE_IntStat_0.Bit4 to 0) Disable the interrupt status (H_SIE_IntEnb_0.Bit4 to 0) <Switching to HOST mode in the ACTIVE state> Clear the interrupt status (H_SIE_IntStat_0.Bit4 to 0) Enable the interrupt status (H_SIE_IntEnb_0.Bit4 to 0) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 343: Port0:141H / Port1:341H H_Sie_Intstat_1 (Sie Host Interrupt Status 1)
HostDeviceSel.HOSTxDEVICE bit is “1” (i.e., in HOST mode), even if power management is ACTIVE. The firmware should perform the following processing to prevent assertion of the interrupt signal XINT by the interrupt status when switching from this state. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 344 Process and clear the interrupt status (H_SIE_IntStat_1.Bit3 to 0) Disable the interrupt status (H_SIE_IntEnb_1.Bit3 to 0) <Switching to HOST mode in ACTIVE state> Clear the interrupt status (H_SIE_IntStat_1.Bit3 to 0) Enable the interrupt status (H_SIE_IntEnb_1.Bit3 to 0) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 345: Port0:143H / Port1:343H H_Frameintstat (Host Frame Interrupt Status )
Set to “1” in the cases shown below, based on the transfer speed. HS: When the host controller issues a micro frame 0 SOF token FS: When the host controller issues an SOF token LS: When the host controller issues keepalive EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 346: Port0:144H / Port1:344H H_Chrintstat (Host Chr Interrupt Status)
Bit0 H_CHaIntStat Indirectly specifies interrupt factors. Set to “1” when the H_CHaIntStat register contains an interrupt factor and the H_CHaIntEnb register bit corresponding to that interrupt factor is enabled. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 347: Port0:145H / Port1:345H H_Ch0Intstat (Host Ch0 Interrupt Status)
This bit is set to “1” upon a condition code stall, data overrun, data underrun or upon three successive retry errors for a transaction. This bit is also set to “1” when the H_CH0Config_0.TranGo bit is cleared by the firmware. In this case, ConditionCode indicates the final transaction results. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 348 This bit is also set to “1” if stop processing ends for a stage other than the status stage or if the status stage ends with a transaction error for the control transfer support function stop processing because the H_CTL_SupportControl register CTL_SupportGo bit is cleared. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 349: Port0:146H / Port1:346H H_Chaintstat (Host Cha Interrupt Status)
This bit is set to “1” when a retry error occurs three times in succession for a transaction, including condition code stalls, data overruns, and data underruns. This bit is also set to “1” when the H_CHaConfig_0.TranGo bit is cleared by the firmware. In this case, ConditionCode indicates the final transaction results. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 350 This bit is also set to “1” if stop processing ends for a transport other than the CSW transport during bulk-only support function stop processing because the H_CHaBO_SupportCtl register BO_SupportGo bit is cleared or if an error is detected in the CSW transport. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 351: Port0:147H / Port1:347H H_Chbintstat (Host Chb Interrupt Status)
This bit is set to “1” when a retry error occurs three times in succession for a transaction, including condition code stalls, data overruns, and data underruns. This bit is also set to “1” when the H_Chx{x=b-e}Config_0.TranGo bit is cleared by the firmware. In this case, ConditionCode indicates the final transaction results. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 352 No transaction was performed because the FIFO free space UFFER VERRUN was smaller than the maximum packet size in an isochronous transfer. • No transaction was performed due to insufficient FIFO valid UFFER NDERRUN data in an isochronous transfer. Other Reserved Bit3-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 353: Port0:150H / Port1:350H H_Sie_Intenb_0 (Host Sie Interrupt Enable)
2: EnDetectRmtWkup 0: Disable 1: Enable 1: EnDetectDevChirpOK 0: Disable 1: Enable 0: EnDetectDevChirpNG 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register H_SIE_IntStat_0 bit using the H_SIE_IntStat_0 register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 354: Port0:151H / Port1:351H H_Sie_Intenb_1(Sie Host Interrupt Enable 1)
2: EnResumeCmp 0: Disable 1: Enable 1: EnSuspendCmp 0: Disable 1: Enable 0: EnResetCmp 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register H_SIE_IntStat_1 bit using the H_SIE_IntStat_1 register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 355: Port0:153H / Por1:353H H_Frameintenb(Host Frame Interrupt Enable )
2: EnPortErr 0: Disable 1: Enable 1: EnFrameNumOver 0: Disable 1: Enable 0: EnSOF 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register H_FrameIntStat bit using the H_FrameIntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 356: Port0:154H / Port1:354H H_Chrintenb(Host Chr Interrupt Enable)
2: EnH_CHcIntStat 0: Disable 1: Enable 1: EnH_CHbIntStat 0: Disable 1: Enable 0: EnH_CHaIntStat 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register H_CHrIntStat bit using the H_CHrIntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 357: Port0:155H / Port1:355H H_Ch0Intenb(Host Ch0 Interrupt Enable)
4: EnChangeCondition 0: Disable 1: Enable 1: EnCTL_SupportCmp 0: Disable 1: Enable 0: EnCTL_SupportStop 0: Disable 1: Enable This permits or prohibits assertion of the MainIntStat register H_CH0IntStat bit using the H_CH0IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 358: Port0:156H / Port1:356H H_Chaintenb (Host Cha Interrupt Enable)
0: Disable 1: Enable 0: Disable 1: EnBO_Support_Cmp 0: Disable 1: Enable 0: EnBO_Support_Stop 0: Disable 1: Enable This permits or prohibits assertion of the H_CHrIntStat register CHaIntStat bit using the H_CHaIntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 359: Port0:157H / Port1:357H H_Chbintenb (Host Chb Interrupt Enable)
1: Enable 159h H_CHdIntEnb 5: EnTranErr 0: Disable 1: Enable 15Ah H_CHeIntEnb 4: EnChangeCondition 0: Disable 1: Enable These permit or prohibit assertion of the H_CHrIntStat register CHx{x=b-e}IntStat bit using the H_CHx{x=b-e}IntStat register interrupt factors. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 360: Port0:160H / Port1:360H H_Negocontrol_0 (Host Negocontrol 0)
“0” once stop processing is completed (requires approximately 6 cycles for a 60 MHz clock). In this case, check that the bit has been changed to “0” before setting H_NegoControl_0.AutoMode GoIDLE or GoDISABLED or before setting H_USB_Test.EnHS_Test. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 361 GoWAIT_CONNECTtoOP (switches continuously from WAIT_CONNECT to OPERATIONAL state) 1100: GoRESETtoOP (switches continuously from RESET to OPERATIONAL state) 1110: GoSUSPENDtoOP (switches continuously from SUSPEND to OPERATIONAL state) 1111: GoRESUMEtoOP (switches continuously from RESUME to OPERATIONAL state) All others: Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 362 Use the following procedure to switch from any state to the IDLE state (using GoIDLE). • Write 0x80 to the H_NegoControl_0 register. • Confirm that the H_NegoControl_0.AutoModeCancel bit has changed to 0. • Write 0x01 to the H_NegoControl_0 register. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 363: Port0:162H / Port1:362H H_Negocontrol_1 (Host Negocontrol 1)
Waits for the device chirp to end after raising the device chirp error status; ends the USB Reset after running the host chirp on completion of the device chirp. Bit0 RmtWkupDetEnb Enables or disables the remote wakeup detection function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 364: Port0:164H / Por1:364H H_Usb_Test (Host Usb_Test)
This test mode enables the host port to receive data in HS mode. Bit2 TEST_J Setting this bit to “1” concurrently with the EnHS_Test bit allows switching to Test_J test mode. This test mode enables the host port to send “J” in HS mode. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 365 PID and CRC are added by SIE when sending test packets. This means that the data written to the FIFO consists of data from the following DATA0 PID data to the CRC16 data of the test packet data described in the USB standard Rev 2.0. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 366: Port0:170H / Port1:370H H_Ch0Setup_0 (Host Ch0 Setup 0)
Sets the higher 8 bits of Wvalue. CH0SETUP_4 Sets the lower 8 bits of WIndex. CH0SETUP_5 Sets the higher 8 bits of WIndex. CH0SETUP_6 Sets the lower 8 bits of WLength. CH0SETUP_7 Sets the higher 8 bits of WLength. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 367: Port0:17Eh-17Fh / Port1:37Eh-37Fh H_Framenumber_H,L
The reset value for this register is the value that can be read by power management in the ACTIVE state. The reset value is read as 0000h in all other states. Bit15-11 Reserved Bit10-0 FrameNumber [10:0] Indicates FrameNumber for the SOF packet to be sent. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 368: Port0:180H / Port1:380H H_Ch0Config_0(Host Channel 0 Configuration0)
This sets the initial value of the toggle sequence bit at the start of a transaction. It also indicates the toggle sequence bit state after the transaction has been started or completed. 0: Toggle 0 1: Toggle 1 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 369 “1.” (To perform a new transaction, clear the FIFO and reset the channel information.) This bit does not need to be set when using the control transfer support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 370: Port0:181H / Port1:381H H_Ch0Config_1(Host Channel 0 Configuration1)
01: OUT − Issues an IN token. 10: IN 11: Reserved − Use of this value is prohibited. This bit does not need to be set when using the control transfer support function. Bit5-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 371: Port0:183H / Port1:383H H_Ch0Maxpktsize (Host Channel 0 Max Packet Size)
This sets the channel CH0 MaxPacketSize for host operations. Bit7 Reserved Bit6-0 MaxPktSize[6:0] This sets the channel CH0 MaxPacketSize. Set to one of the following: LS: 8bytes FS: 8, 16, 32, 64 bytes HS: 64 bytes All other settings are prohibited. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 372: Port0:186H-187H / Port1:386H-387H H_Ch0Totalsize_H,L
A zero-length packet is issued when an OUT transaction is performed with TotalSize = 0. This register does not need to be set when performing a SETUP transaction or when using the control transfer support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 373: Port0:188H / Port1:388H H_Ch0Hubadrs (Host Channel 0 Hub Address)
It can be set to any value from 0 to 15. Bit3 Reserved Bit2-0 Port[2:0] This sets the port number of the hub to which the function performing the transfer over channel CH0 connects. It can be set to any value from 0 to 7. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 374: Port0:189H / Port1:389H H_Ch0Funcadrs (Host Channel 0 Function Address)
It can be set to any value from 0 to 15. Bit3-0 EP_Number[3:0] This sets the endpoint number for the transfer over channel CH0. It can be set to any value from 0 to 15. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 375: Port0:18Bh / Port1:38Bh H_Ctl_Supportcontrol (Host Controltransfer Support Control)
If a packet error is detected in mid-sequence, the H_CH0IntStat register CTL_SupportStop bit is set, and the transaction stops. In this case, the cause is set to the ConditionCode register to enable inspection. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 376 The CTL_SupportCmp bit is set if the control transfer ends normally in the status stage. In all other cases, the CTL_SupportStop bit is set. Refer to CTL_SupportState for the stage in which the control transfer stopped. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 377: Port0:18Eh / Port1:38Eh H_Ch0Conditioncode (Host Channel 0 Condition Code)
The PID received is invalid or no PID value is defined. • The data toggle included in the data packet from the endpoint fails to match the expected value (toggle mismatch). Other Reserved Bit3-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 378: Port0:190H / Port1:390H H_Chaconfig_0(Host Channel A Configuration0)
This sets the initial value of the toggle sequence bit at the start of a transaction. It also indicates the toggle sequence bit state after the transaction has been started or completed. 0: Toggle 0 1: Toggle 1 This bit does not need to be set when using the bulk-only support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 379 “1.” (To perform a new transaction, clear the FIFO and reset the channel information.) This bit does not need to be set when using the bulk-only support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 380: Port0:191H / Port1:391H H_Chaconfig_1(Host Channel A Configuration1)
H_CHaTotalSizeHH to LL registers ends at exactly the Max Packet Size. This bit is enabled only for OUT transfers. Bit2-1 Reserved Bit0 TotalSizeFree Setting this bit to “1” cancels any restrictions on transfer size, regardless of H_CHaTotalSizeHH to LL register settings. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 381: Port0:192H-193H / Port1:392H-393H H_Chamaxpktsize_H,L
These set the channel CHa MaxPacketSize. Set to one of the following: FS: 8, 16, 32, 64 bytes (32 or 64 bytes when using bulk-only support function) HS: 512 bytes All other settings are prohibited. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 382: Port0:194H-195H / Port1:394H-395H H_Chatotalsize_Hh,Hl
15: TotalSize[15] 14: TotalSize[14] 13: TotalSize[13] 12: TotalSize[12] 11: TotalSize[11] 10: TotalSize[10] 9: TotalSize[9] 8: TotalSize[8] Total Size Low 0000h 7: TotalSize[7] 6: TotalSize[6] 5: TotalSize[5] 4: TotalSize[4] 3: TotalSize[3] 2: TotalSize[2] 1: TotalSize[1] 0: TotalSize[0] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 383 The remaining transfer quantity can be read by reading these registers after the transaction has been started by the H_CHaConfig_0 register TranGo bit. A zero-length packet is issued when an OUT transaction is performed with TotalSize = 0. This register does not need to be set when using the bulk-only support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 384: Port0:198H / Port1:398H H_Chahubadrs (Host Channel A Hub Address)
It can be set to any value from 0 to 15. Bit3 Reserved Bit2-0 Port[2:0] This sets the port number of the hub to which the function performing the transfer over channel CHa connects. It can be set to any value from 0 to 7. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 385: Port0:199H / Port1:399H H_Chafuncadrs (Host Channel A Function Address)
This sets the endpoint number for the transfer over channel CHa. It can be set to any value from 0 to 15. This bit does not need to be set when using the bulk-only support function. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 386: Port0:19Ah / Port1:39Ah H_Chabo_Supporotctl
H_CHaIntStat register BO_SupportStop bit is set and the transaction stops. In this case, the cause is set to the H_CHaConditionCode register to enable inspection. If the ConditionCode value is “000” when the H_CHaIntStat register BO_SupportStop bit is set to “1,” the CSW value is incorrect. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 387 The transport can be stopped by clearing this bit while running the bulk-only support function. The BO_SupportCmp bit is set if the CSW transport ends normally here. The BO_SupportStop bit is set in all other cases. Refer to BO_TransportState for the stopped transport. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 388: Port0:19Bh / Port1:39Bh H_Chabo_Csw_Rcvsize
The amount of data received can be checked using this register when fewer than 13 bytes of data have been received in CSW transport. This register value has no meaning if a handshake was received in CSW transport or other than for CSW transport. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 389: (Host Cha Bulk Only Transfer Support Out Endpoint Control)
The H_CBW_Control register BO_SupportGo bit is set to “1” and the endpoint number of the transfer destination device for OUT-direction transfer (CBW transport or Data OUT transport) is set using the bulk-only support function. It can be set to any value from 0 to 15. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 390 The H_CBW_Control register BO_SupportGo bit is set to “1” and the endpoint number of the transfer destination device for IN-direction transfer (CSW transport or Data IN transport) is set using the bulk-only support function. It can be set to any value from 0 to 15. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 391 The PID received is invalid or no PID value is defined. • The data toggle included in the data packet from the endpoint fails to match the expected value (toggle mismatch). Other Reserved Bit3-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 392 This sets the initial value of the toggle sequence bit at the start of a transaction. It also indicates the toggle sequence bit state after the transaction has been started or completed. 0: Toggle 0 1: Toggle 1 EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 393 This allows resumption of the transaction from the point at which it was stopped by resetting this bit to “1.” (To perform a new transaction, clear the FIFO and reset the channel information.) EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 394 AutoZerolen Setting this bit to “1” automatically adds a zero-length packet after the transfer size set in the H_CHx{x=b-e}TotalSizeHH to LL registers ends at exactly the MaxPacketSize. This bit is enabled only for OUT transfers. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 395 TotalSize value is “0.” For OUT transfers, the data packet size will be the smaller of MaxPktSize and TotalSize. For IN transfers, the expected data packet size will be the smaller of MaxPktSize and TotalSize. 11: Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 396 FS: 8, 16, 32, 64 bytes HS: 512 bytes The transfer size can be set as follows when using this channel for interrupt transfers. LS: Up to 8 bytes FS: Up to 64 bytes HS: Up to 1,024 bytes EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 397 3. Register Details The transfer size can be set as follows when using this channel for isochronous transfer. FS: Up to 1,023 bytes HS: Up to 1,024 bytes All other settings are prohibited. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 398 H_CHdTotalSize_HH,HL 13: TotalSize[29] 1D4h-1D5h H_CHeTotalSize_HH,HL 12: TotalSize[28] 11: TotalSize[27] 10: TotalSize[26] 9: TotalSize[25] 8: TotalSize[24] Total Size High 0000h 7: TotalSize[23] 6: TotalSize[22] 5: TotalSize[21] 4: TotalSize[20] 3: TotalSize[19] 2: TotalSize[18] 1: TotalSize[17] 0: TotalSize[16] EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 399 The remaining transfer quantity can be read by reading these registers after the transaction has been started by the H_CHx{x=b-e}Config_0 register TranGo bit. A zero-length packet is issued when an OUT transaction is performed with TotalSize = 0. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 400 It can be set to any value from 0 to 15. Bit3 Reserved Bit2-0 Port[2:0] This sets the port number of the hub to which the function performing the transfer over channel CHx{x=b-e} connects. It can be set to any value from 0 to 7. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 401: Port0:1D9H / Port1:3D9H H_Chefuncadrs (Host Channel D Function Address)
It can be set to any value from 0 to 15. Bit3-0 EP_Number[3:0] This sets the endpoint number for the transfer over channel CHx{x=b-e}. It can be set to any value from 0 to 15. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 402: Port0:1Aah-1Abh / Port1:3Aah-3Abh H_Chbinterval_H,L
Interval[10:3] Frame − Specifies the interval in ms units. It can be set to any value from 1 to 255 frames. Interval[2:0] must be set entirely to “0” when setting this bit. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 403: 14Ch H_Chbtranpause(Host Channel B Transaction Pause)
H_CHx{x=b-e}Config_0 TranGo bit is set to “1.” If this channel is set for interrupt or isochronous transfers, the transfer cycle is maintained, even if no transactions can be performed because the bit is set to “1.” EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 404: Port0:1Aeh / Port1:3Aeh H_Chbconditioncode (Host Channel B Condition Code)
The data packet received is less than the maximum packet NDERRUN size; the data size is less than the IRP (TotalSize). Treated as a retry error if CRC error and bit stuffing error are detected simultaneously. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 405 No transaction was performed because the FIFO free space UFFER VERRUN was smaller than the maximum packet size in an isochronous transfer. • No transaction was performed due to insufficient FIFO valid UFFER NDERRUN data in an isochronous transfer. Other Reserved Bit3-0 Reserved EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 406: Appendix A: Connection To Little-Endian Cpu
For registers larger than Short, use divided access with Short and cast in the CPU memory for use. The registers for which odd and even addresses are swapped are shown below for CPU_Endian=“1” (little endian). Reading and writing is possible to/from CD[15:0] for these registers with the 16-bit registers arranged unchanged. EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 407 AREA0StartAdrs_L 0x081 AREA0StartAdrs_H 0x082 AREA0EndAdrs_H 0x082 AREA0EndAdrs_L 0x083 AREA0EndAdrs_L 0x083 AREA0EndAdrs_H 0x084 AREA1StartAdrs_H 0x084 AREA1StartAdrs_L 0x085 AREA1StartAdrs_L 0x085 AREA1StartAdrs_H 0x086 AREA1EndAdrs_H 0x086 AREA1EndAdrs_L 0x087 AREA1EndAdrs_L 0x087 AREA1EndAdrs_H 0x088 AREA2StartAdrs_H 0x088 AREA2StartAdrs_L 0x089 AREA2StartAdrs_L 0x089 AREA2StartAdrs_H EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 408 D_AlarmOUT_IntStat_L 0x0BF D_AlarmOUT_IntStat_H 0x0CC D_AlarmIN_IntEnb_H 0x0CC D_AlarmIN_IntEnb_L 0x0CD D_AlarmIN_IntEnb_L 0x0CD D_AlarmIN_IntEnb_H 0x0CE D_AlarmOUT_IntEnb_H 0x0CE D_AlarmOUT_IntEnb_L 0x0CF D_AlarmOUT_IntEnb_L 0x0CF D_AlarmOUT_IntEnb_H 0x0EE D_FrameNumber_H 0x0EE D_FrameNumber_L 0x0EF D_FrameNumber_L 0x0EF D_FrameNumber_H 0x0F8 D_EPaMaxSize_H 0x0F8 D_EPaMaxSize_L 0x0F9 D_EPaMaxSize_L 0x0F9 D_EPaMaxSize_H EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 409 D_EnEP_OUT_ISO_H 0x12E D_EnEP_OUT_ISO_L 0x12F D_EnEP_OUT_ISO_L 0x12F D_EnEP_OUT_ISO_H Host register (HOSTxDEVICE=1) Host register (HOSTxDEVICE=1) 0x17E H_FrameNumber_H 0x17E H_FrameNumber_L 0x17F H_FrameNumber_L 0x17F H_FrameNumber_H 0x182 0x182 H_CH0MaxPktSize 0x183 H_CH0MaxPktSize 0x183 0x186 H_CH0TotalSize_H 0x186 H_CH0TotalSize_L 0x187 H_CH0TotalSize_L 0x187 H_CH0TotalSize_H EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 410 H_CHcTotalSize_LH 0x1B6 H_CHcTotalSize_LL 0x1B7 H_CHcTotalSize_LL 0x1B7 H_CHcTotalSize_LH 0x1BA H_CHcInterval_H 0x1BA H_CHcInterval_L 0x1BB H_CHcInterval_L 0x1BB H_CHcInterval_H 0x1C2 H_CHdMaxPktSize_H 0x1C2 H_CHdMaxPktSize_L 0x1C3 H_CHdMaxPktSize_L 0x1C3 H_CHdMaxPktSize_H 0x1C4 H_CHdTotalSize_HH 0x1C4 H_CHdTotalSize_HL 0x1C5 H_CHdTotalSize_HL 0x1C5 H_CHdTotalSize_HH 0x1C6 H_CHdTotalSize_LH 0x1C6 H_CHdTotalSize_LL EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 411 H_CHdInterval_L 0x1CB H_CHdInterval_H 0x1D2 H_CHeMaxPktSize_H 0x1D2 H_CHeMaxPktSize_L 0x1D3 H_CHeMaxPktSize_L 0x1D3 H_CHeMaxPktSize_H 0x1D4 H_CHeTotalSize_HH 0x1D4 H_CHeTotalSize_HL 0x1D5 H_CHeTotalSize_HL 0x1D5 H_CHeTotalSize_HH 0x1D6 H_CHeTotalSize_LH 0x1D6 H_CHeTotalSize_LL 0x1D7 H_CHeTotalSize_LL 0x1D7 H_CHeTotalSize_LH 0x1DA H_CHeInterval_H 0x1DA H_CHeInterval_L 0x1DB H_CHeInterval_L 0x1DB H_CHeInterval_H EPSON S2R72V18 Technical Manual (Rev.1.00)
Page 412 Revision History Revision History (Rev. 1.00) Revision details Date Section Rev. Type Details (old version) 10/12/2007 0.79 All pages Newly established 7/15/2008 1.00 Revision “Disconnection detection is performed for the uSOF(HS_SOF) EOP time period, and the device is determined to be disconnected if identified as disconnected three times in succession”...
Page 413 Phone: +49-89-14005-0 FAX: +49-89-14005-110 12/F, Dawning Mansion, Keji South 12th Road, Hi- Tech Park, Shenzhen Phone: +86-755-2699-3828 FAX: +86-755-2699-3838 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110 Phone: +886-2-8786-6688 FAX: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD.

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