Interrupt Request - NEC V850E/MS1 UPD703100 User Manual

32-/16-bit single-chip microcontrollers
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10.2.4 Interrupt request

UARTn generates the following three types of interrupt requests (n = 0, 1).
• Receive error interrupt (INTSERn)
• Reception complete interrupt (INTSRn)
• Transmission complete interrupt (INTSTn)
The priority order of these three interrupts is, from high to low: receive error interrupt, reception complete interrupt,
transmission complete interrupt.
(1) Receive error interrupt (INTSERn)
In the reception enabled state, a receive error interrupt is generated by ORing the three receive errors.
In the reception disabled state, no receive error interrupt is generated.
(2) Reception completion interrupt (INTSRn)
In the reception enabled state, a reception complete interrupt is generated when data is shifted into the receive
shift register and transferred to the receive buffer.
This reception complete interrupt request is also generated when a receive error has occurred, but the receive
error interrupt has a higher servicing priority.
In the reception disabled state, no reception complete interrupt is generated.
(3) Transmission completion interrupt (INTSTn)
As this UARTn has no transmit buffer, a transmission complete interrupt is generated when one frame of
transmit data containing a 7-, 8-, or 9-bit character is shifted out of the transmit shift register.
A transmission complete interrupt is output at the start of transmission of the last bit of transmit data.
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CHAPTER 10 SERIAL INTERFACE FUNCTION
Table 10-1. Default Priority of Interrupt
Interrupt
Receive error
Reception complete
Transmission complete
User's Manual U12688EJ4V0UM00
Priority
1
2
3

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