Features - NEC V850E/MS1 UPD703100 User Manual

1.2 Features

{ Number of instructions:
{ Minimum instruction execution time:
{ General registers:
{ Instruction set:
{ Memory space:
{ External bus interface:
{ Internal memory:
{ Interrupt/exception:
{ Memory access controller:
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CHAPTER 1 INTRODUCTION
81
25 ns (at internal 40 MHz) ... µ PD703100-40, 703100A-40
30 ns (at internal 33 MHz) ... other than above
32 bits × 32
Upwardly compatible with V850 CPU
Signed multiplication (16 bits × 16 bits → 32 bits or 32 bits × 32 bits →
64 bits): 1 to 2 clocks
Saturated operation instructions (with overflow/underflow detection
function)
32-bit shift instructions: 1 clock
Bit manipulation instructions
Load/store instructions with long/short format
Signed load instructions
32 MB linear address space (common program/data use)
Chip select output function: 8 spaces
Memory block division function: 2, 4, 8 MB/block
Programmable wait function
Idle state insertion function
16-bit data bus (address/data multiplexed)
16-/8-bit bus sizing function
Bus hold function
External wait function
Part Number
µ PD703100, 703100A
µ PD703101, 703101A
µ PD703102, 703102A
µ PD70F3102, 70F3102A
External interrupts: 25 (including NMI)
Internal interrupts: 47 sources
Exceptions: 1 source
Eight levels of priorities can be set.
DRAM controller (Compatible with EDO DRAM and high-speed page
DRAM)
Page-ROM controller
User's Manual U12688EJ4V0UM00
Internal ROM
None
96 Kbytes (Mask ROM)
128 Kbytes (Mask ROM)
128 Kbytes (Flash memory)
Internal RAM
4 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes