NEC V850E/MS1 UPD703100 User Manual page 447

RD............................................................................ 57
Real-time pulse unit ............................................... 247
Receive buffers 0, 0L, 1, 1L ................................... 292
Receive error interrupt ........................................... 294
Reception completion interrupt............................... 294
Recommended connection of unused pins .............. 65
Refresh control function ......................................... 153
Refresh control registers 0 to 3 .............................. 153
Refresh timing ........................................................ 157
Refresh wait control register .................................. 156
REFRQ..................................................................... 62
REG0 to REG7....................................................... 101
Relationship between analog input voltage and
A/D conversion results ........................................... 322
Relationship between programmable wait and
external wait ........................................................... 114
REN0 to REN3 (DRST register) ............................. 173
RENn (RFCn register) (n = 0 to 3) ......................... 153
RESET ..................................................................... 64
Reset functions ...................................................... 409
RFC0 to RFC3 ....................................................... 153
RHC0n, RHC1n (n = 0 to 3) ................................... 140
RHD0 to RHD3....................................................... 140
RIn0 to RIn5 (n = 0 to 3)......................................... 154
ROMC ................................................................... 130
ROM-less modes 0, 1 .............................................. 74
RPC0n, RPC1n (n = 0 to 3).................................... 139
RRW0, RRW1 ........................................................ 156
RWC ...................................................................... 156
RXB0, RXB0L, RXB1, RXB1L................................ 292
RXBn0 to RXBn7 (n = 0, 1) .................................... 292
RXD0, RXD1 ............................................................ 51
RXE0, RXE1 .......................................................... 287
RXEB0, RXEB1...................................................... 292
[S]
S............................................................................... 73
SA0 to SA15........................................................... 164
SA16 to SA25......................................................... 163
SAD0, SAD1 .......................................................... 168
SAT .......................................................................... 73
Scan mode ............................................................. 328
SCK0, SCK1 ............................................................ 51
SCK2........................................................................ 52
SCK3........................................................................ 59
SCLS00, SCLS01, SCLS10, SCLS11.................... 289
Securing oscillation stabilization time..................... 244
SEIC0, SEIC1 ........................................................ 217
APPENDIX C INDEX
SEIF0, SEIF1 ......................................................... 217
Select mode ........................................................... 325
Self-refresh functions ............................................. 158
SEMK0, SEMK1..................................................... 217
SEPR0n, SEPR1n (n = 0 to 2) ............................... 217
Serial I/O shift registers 0 to 3................................ 303
Serial interface function.......................................... 283
SI0, SI1 .................................................................... 51
SI2............................................................................ 52
SI3............................................................................ 59
Single-chip modes 0, 1............................................. 74
Single-step transfer mode ...................................... 180
Single transfer mode .............................................. 179
SIO0 to SIO3.......................................................... 303
SIOn0 to SIOn7 (n = 0 to 3) ................................... 303
SL0, SL1 ................................................................ 289
SO0, SO1................................................................. 51
SO2.......................................................................... 52
SO3.......................................................................... 59
Software exception ................................................ 222
Software STOP mode ............................................ 242
SOT0, SOT1 .......................................................... 291
Specific registers.................................................... 100
SRAM interface...................................................... 125
SRAM connections ................................................ 125
SRIC0, SRIC1........................................................ 217
SRIF0, SRIF1......................................................... 217
SRMK0, SRMK1 .................................................... 217
SRPR0n, SRPR1n (n = 0 to 2)............................... 217
SRW2 to SRW0 ..................................................... 156
Stack pointer ............................................................ 71
Status saving register during CALLT execution ....... 72
Status saving register during exception trap ............ 72
Status saving register during interrupt...................... 72
Status saving register during NMI ............................ 72
STG0 to STG3 ....................................................... 170
STIC0, STIC1......................................................... 217
STIF0, STIF1 ......................................................... 217
STMK0, STMK1 ..................................................... 217
STP ........................................................................ 237
STPR0n, STPR1n (n = 0 to 2)................................ 217
SYS........................................................................ 102
System register set .................................................. 72
System status register............................................ 102
[T]
TBC........................................................................ 246
TBCS ..................................................................... 237
User's Manual U12688EJ4V0UM00
447