5.3 DRAM Controller
5.3.1 Features
{ Generates the RAS, LCAS and UCAS signals.
{ Can be connected directly to high-speed page DRAM and EDO DRAM.
{ Supports the RAS hold mode.
{ 4 types of DRAM can be assigned to 8 memory block spaces.
{ Can handle 2CAS type DRAM
{ Can be switched between row and column address multiplex widths.
{ Waits (0 to 3 waits) can be inserted at the following timings.
• Row address precharge wait
• Row address hold wait
• Data access wait
• Column address precharge wait
{ Supports CBR refresh and CBR self-refresh.
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CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
User's Manual U12688EJ4V0UM00