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8.6 Securing Oscillation Stabilization Time
8.6.1 Specifying securing of oscillation stabilization time
There are 2 methods for specifying securing of time for stabilizing the oscillator in the stop mode after releasing
the software STOP mode.
(1) If securing time by the internal time base counter (NMI pin input)
If the active edge of the NMI pin is input, the software STOP mode is released. When the inactive edge is
input to the pin, the time base counter (TBC) starts counting, and at that count time, the time until the clock
output from the oscillator stabilizes is secured.
Oscillation stabilization time ≅ (Active level width after NMI input active edge detection) + (TBC count time)
After the proper time, start internal system clock output and branch to the NMI interrupt handler address.
Oscillation waveform
Internal system clock
CLKOUT (output)
STOP state
NMI (input)
The NMI pin should normally be set at the inactive level (for example, so that it changes to high level when
the active edge is specified to be falling).
Furthermore, if an operation is executed which sets the system in the STOP mode for a time until an interrupt
is received from the CPU from the NMI active edge input timing, the software STOP mode is quickly released.
In the case of the PLL mode and the resonator connection mode (CESEL bit of PSC register = 0), program
execution starts after the oscillation stabilization time is secured by the time base counter after input of the
NMI pin's inactive edge.
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CHAPTER 8 CLOCK GENERATOR FUNCTIONS
Software STOP mode setting
Oscillator stopped
User's Manual U12688EJ4V0UM00
Time base counter
current time
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