NEC V850E/MS1 UPD703100 User Manual page 302

Bit Position Bit Name
1, 0 CLSn1,
CLSn0
Cautions 1. When setting the CLSn1 and CLSn0 bits, do so in the transmission/reception disabled
(CTXEn bit = CRXEn bit = 0) state. If the CLSn1 and CLSn0 bits are set in a state other
than transmission/reception disabled, subsequent operation may not be normal.
2. If the values set in bits 0 to 2 of these registers are changed while CSIn is transmitting or
receiving, the operation of CSIn is not guaranteed.
Remark n = 0 to 3
302
CHAPTER 10 SERIAL INTERFACE FUNCTION
Clock Source
Specifies the serial clock.
CLSn1 CLSn0
0 0 External clock
0 1 Internal
clock
1 0
1 1
Notes 1. Refer to 10.4 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)
concerning setting of the BPRMm registers (m = 0 to 2).
φ /4 and φ /2 are divider signals ( φ : Internal system clock).
2.
User's Manual U12688EJ4V0UM00
Function
Serial Clock Specification
Specified by the BPRMm
Note 1
register
φ /4
Note 2
φ /2
Note 2
SCK Pin
Input
Output
Output
Output