Control Registers - NEC V850E/MS1 UPD703100 User Manual

CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)

9.3 Control Registers

(1) Timer unit mode registers 10 to 15 (TUM10 to TUM15)
The TUM1n register is a register which controls the operation of timer 1 and specifies the capture/compare
register operation mode (n = 0 to 5).
These registers can be read/written in 16-bit units.
15 14 13
TUM10 0 0 OST0
TUM11 0 0 OST1
TUM12 0 0 OST2
TUM13 0 0 OST3
TUM14 0 0 OST4
TUM15 0 0 OST5
Bit Position Bit Name
13 OSTn
12 ECLR1n
Remark n = 0 to 5
254
12 11 10 9 8 7
ECLR TES TES CES CES CMS
10 101 100 101 100 103
ECLR TES TES CES CES CMS
11 111 110 111 110 113
ECLR TES TES CES CES CMS
12 121 120 121 120 123
ECLR TES TES CES CES CMS
13 131 130 131 130 133
ECLR TES TES CES CES CMS
14 141 140 141 140 143
ECLR TES TES CES CES CMS
15 151 150 151 150 153
Overflow Stop
Specifies the timer's operation after overflow. This flag is valid only in TM1n.
0: Timer continues to count up after timer overflow.
1: Timer holds 0000H and is in the stopped state after timer overflow.
When this happens, the CE1 bit in the TMC1n register remains at 1.
Counting up resumes with the next operation.
When ECLR1n = 0: 1 write operation to the CE1n bit.
When ECLR1n = 1: Trigger input to the timer clear pin (TCLR1n).
External Input Timer Clear
Clearing of the timer is enabled by the TM1n external clear input (TCLR1n).
0: Timer is not cleared by an external input.
1: TM1n is cleared by an external input.
Counting up starts after clearing.
User's Manual U12688EJ4V0UM00
6 5 4 3 2 1
CMS CMS CMS IMS IMS IMS
102 101 100 103 102 101
CMS CMS CMS IMS IMS IMS
112 111 110 113 112 111
CMS CMS CMS IMS IMS IMS
122 121 120 123 122 121
CMS CMS CMS IMS IMS IMS
132 131 130 133 132 131
CMS CMS CMS IMS IMS IMS
142 141 140 143 142 141
CMS CMS CMS IMS IMS IMS
152 151 150 153 152 151
Function
0
IMS
Address After reset
100
FFFFF240H 0000H
IMS
110
FFFFF260H 0000H
IMS
120
FFFFF280H 0000H
IMS
130
FFFFF2A0H 0000H
IMS
140
FFFFF2C0H 0000H
IMS
150
FFFFF2E0H 0000H