NEC V850E/MS1 UPD703100 User Manual page 150

TRPW
CLKOUT
A0 to A23
BCYST
CSn/RASn
RD
OE
WE
UWR/UCAS
LWR/LCAS
IORD
IOWR
D0 to D15
Optional
WAIT
Remarks 1. This is the timing in the following cases (×× = 00 to 03, 10 to 13).
Number of waits according to bit RPC×× (TRPW): 1
Number of waits according to bit RHC×× (TRHW): 1
Number of waits according to bit DAC×× (TDAW): 1
Number of waits according to bit CPC×× (TCPW): 1
2. The broken lines indicate high impedance.
3. n = 0 to 7
150
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION
Figure 5-9. EDO DRAM Access Timing (4/4)
(d) Write timing 2
T1 TRHW T2 TDAW TCPW
Row address Column address
Data
User's Manual U12688EJ4V0UM00
TB TDAW TCPW
Column address
Data
TB TDAW TE
Column address
Data