NEC V850E/MS1 UPD703100 User Manual page 334

(b) 4-trigger mode (Timer trigger select: 1-buffer, 4-trigger)
One analog input is A/D converted four times using four match interrupt signals (INTCC110 to INTCC113)
as triggers and the results are stored in one ADCRn register. The INTAD interrupt is generated with each
A/D conversion, and the CS bit of the ADM0 register is reset (0). The results of one A/D conversion are
held by the ADCRn register until the next A/D conversion ends. Perform transmission of the conversion
results to the memory and other operations using the INTAD interrupt after each A/D conversion ends.
Trigger
INTCC110 interrupt
INTCC111 interrupt
INTCC112 interrupt
INTCC113 interrupt
When the TM11 is set to the 1-shot mode, A/D conversion ends after four conversions. To restart A/D
conversion, input the valid edge to the TCLR11 pin or write 1 to the CE11 bit of the TMC11 register to
restart the TM11. When the first match interrupt after TM11 is restarted is generated, the CS bit is set (1)
and A/D conversion is started.
When set to the loop mode, unless the CE bit of the ADM0 register is set to 0, A/D conversion is repeated
each time the match interrupt is generated.
The match interrupts (INTCC110 to INTCC113) can be generated in any order. The same trigger, even
when it enters several times consecutively, is accepted as a trigger each time.
Figure 11-10. Example of 4-Trigger Mode (Timer Trigger Select 1-Buffer 4-Trigger) Operation
No particular
INTCC110
INTCC111
INTCC112
INTCC113
(1) CE bit of ADM0 is set to 1 (enable)
(2) CC112 compare generation (random)
(3) ANI2 A/D conversion
(4) Conversion result is stored in ADCR2
(5) INTAD interrupt generation
(6) CC111 compare generation (random)
(7) ANI2 A/D conversion
(8) Conversion result is stored in ADCR2
(9) INTAD interrupt generation
334
CHAPTER 11 A/D CONVERTER
Analog Input A/D Conversion Result Register
ANIn ADCRn
ANIn ADCRn
ANIn ADCRn
ANIn ADCRn
ANI0
ANI1
order
ANI2 (×4)
ANI3
User's Manual U12688EJ4V0UM00
(n = 0 to 3)
(×4)
A/D converter
(10) CC113 compare generation (random)
(11) ANI2 A/D conversion
(12) Conversion result is stored in ADCR2
(13) INTAD interrupt generation
(14) CC110 compare generation (random)
(15) ANI2 A/D conversion
(16) Conversion result is stored in ADCR2
(17) INTAD interrupt generation
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7