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CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)
(5) External interrupt mode registers 1 to 6 (INTM1 to INTM6)
If CC1n0 to CC1n3 of TM1n are used as a capture register, the active edge of the external interrupt INTP1n0
to
INTP1n3
signals
INTERRUPT/EXCEPTION PROCESSING FUNCTION) (n = 0 to 5).
(6) Timer overflow status register (TOVS)
This interrupts overflow flags from TM10 to TM15, TM40, and TM41.
The register can be read/written in 8- or 1-bit units.
By setting and resetting the TOVS register through software, polling of overflow occurrences can be
accomplished.
7
6
TOVS
OVF41
OVF40
Bit Position
Bit Name
7 to 0
OVF41, OVF40,
OVF15 to OVF10
Remark n = 0 to 5
is
detected
as
a
capture
5
4
3
OVF15
OVF14
OVF13
Overflow Flag
This is the overflow flag for TM41, TM40 and TM1n.
0: No overflow is generated.
1: Overflow is generated.
Caution
Interrupt requests (INTOV1n) for the interrupt controller are
generated in synch with an overflow from TM1n, but because
interrupt operations and the TOVS register are independent, the
overflow flag (OVF1n) from TM1n can be operated by software
just like other overflow flags.
At this time, the interrupt request flag (OVF1n) corresponding to
INTOV1n is not affected.
During CPU access interval, transfers to the TOVS register cannot be made.
Therefore, even if an overflow is generated during a readout from the TOVS
register, the flag's value does not change and it is reflected in the next read
operation.
User's Manual U12688EJ4V0UM00
trigger
(for
details,
2
1
0
OVF12
OVF11
OVF10
Function
refer
to
CHAPTER
7
Address
After reset
FFFFF230H
00H
261
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