Control Registers - NEC V850E/MS1 UPD703100 User Manual

10.2.3 Control registers

(1) Asynchronous serial interface mode registers 00, 01, 10, 11 (ASIM00, ASIM01, ASIM10, ASIM11)
These registers specify the UART0 and UART1 transfer mode.
These registers can be read/written in 8- or 1-bit units.
7 6
ASIM00 TXE0 RXE0
ASIM10 TXE1 RXE1
Bit Position Bit Name
7, 6 TXEn,
RXEn
Remark n = 0, 1
CHAPTER 10 SERIAL INTERFACE FUNCTION
5 4 3
PS01 PS00 CL0
PS11 PS10 CL1
Transmit/Receive Enable
Specifies the transmission/reception enable status/disable status.
TXEn RXEn
0 0
0 1
1 0
1 1
When reception is disabled, the receive shift register does not detect the start bit. The
receive buffer contents are held without shift-in processing or transmit processing to the
receive buffer being performed.
While in the reception enabled state, the receive shift operation is started in
synchronization with detection of the start bit and after 1 frame of data has been
received, the contents of the receive shift register are transmitted to the receive buffer.
Also, the reception complete interrupt (INTSRn) is generated in synchronization with
transmission to the receive buffer. The TXDn pin becomes high impedance when
transmission is disabled and a high level is output if it is not transmitting when
transmission is enabled.
User's Manual U12688EJ4V0UM00
2 1 0
SL0 SCLS01 SCLS00
SL1 SCLS11 SCLS10
Function
Operation
Transmission/reception disabled (CSIn selected)
Reception enabled
Transmission enabled
Transmission/reception enabled
Address After reset
FFFFF0C0H 80H
FFFFF0D0H 80H
287