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Notes 12. In this instruction, for convenience of mnemonic description, the source register is made reg2, but the
reg1 field is used in the op code. Therefore, the meaning of register specification in the mnemonic
description and in the op code differs from other instructions.
r r r r r = regID specification
RRRRR = reg2 specification
13. i i i i i: Lower 5 bits of imm9.
I I I I: Lower 4 bits of imm9.
14. In the case of r = w (the lower 32 bits of the results are not written in the register) or w = r0 (the higher
32 bits of the results are not written in the register), 1.
15. sp/imm: specified by bits 19 and 20 of the sub op code.
16. ff = 00: Load sp in ep.
01: Load sign expanded 16-bit immediate data (bits 47 to 32) in ep.
10: Load 16-bit logically left shifted 16-bit immediate data (bits 47 to 32) in ep.
11: Load 32-bit immediate data (bits 63 to 32) in ep.
17. If imm = imm32, N + 3 blocks.
18. r r r r r : Other than 00000.
19. ddddddd: Higher 7 bits of disp8.
20. dddd: Higher 4 bits of disp5.
21. dddddd: Higher 6 bits of disp8.
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APPENDIX B INSTRUCTION SET LIST
User's Manual U12688EJ4V0UM00
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