NEC V850E/MS1 UPD703100 User Manual page 305

(2) Transmission/reception enabled
CSIn each have only one 8-bit shift register and do not have any buffers, so basically, they conduct
transmission and reception simultaneously (n = 0 to 3).
(a) Transmission/reception enable conditions
Setting of the CSIn transmission and reception enable conditions is accomplished by the CTXEn and
CRXEn bits of the CSIMn registers.
However, it is necessary to set TXE0 bit = RXE0 bit = 0 in the ASIM00 register in the case of CSI0 and to
set TXE1 bit = RXE1 bit = 0 in the ASIM10 register in the case of CSI1.
Remark
Remarks 1. If the CTXEn bit = 0, CSIn becomes as follows.
• CSI0, CSI1: The serial output becomes high impedance or UARTn output (TXDn).
• CSI2, CSI3: The serial output becomes high impedance.
2. If the CRXEn bit = 0, the shift register input becomes 0.
If the CRXEn bit = 1, the serial input is input to the shift register.
3. In order to receive transmit data itself and check if a bus conflict is occurring, set CTXEn
bit = CRXEn bit = 1.
(3) Starting transmit/receive operations
Transmit or receive operations are started by reading/writing the SIOn registers. Transmission/reception start
control is carried out by setting the CTXEn and CRXEn bits of the CSIMn registers as shown below (n = 0 to
3).
Remark
When the CTXEn bit is 0, the SIOn register is read/write, and even if it is set (1) afterward, transfer does not
start.
Also, when the CTXEn bit is 0, if the CRXEn bit is changed from 0 to 1, the serial clock is generated and
receive operation starts.
CHAPTER 10 SERIAL INTERFACE FUNCTION
CTXEn CRXEn
0 0 Transmission/reception disabled
0 1 Reception enabled
1 0 Transmission enabled
1 1 Transmission/reception enabled
n = 0 to 3
If the CTXEn bit = 1, the shift register data is output.
CTXEn CRXEn
0 0 Doesn't start
0 1 Reads the SIOn register
1 0 Writes to the SIOn register
1 1 Writes to the SIOn register
0 → 1
0 Rewrites the CRXEn bit
n = 0 to 3
User's Manual U12688EJ4V0UM00
Transmit/Receive Operation
Start Condition
305