NEC V850E/MS1 UPD703100 User Manual page 85

(2) Internal RAM area
4 KB of memory, addresses 3FFE000H to 3FFEFFFH, is provided as a physical internal RAM area.
(3) Internal peripheral I/O area
4 KB of memory, addresses 3FFF000H to 3FFFFFFH, is provided as an internal peripheral I/O area.
Peripheral I/O registers associated with the operation mode specification and the state monitoring for the
internal peripheral I/O are all memory-mapped to the internal peripheral I/O area. Program fetches are not
allowed in this area.
Cautions 1. The least significant bit of an address is not decoded. If byte access is executed in the
register at an odd address (2n + 1), the register at the even address (2n) will be accessed
because of the hardware specification.
2. In the V850E/MS1, no registers exist which are capable of word access, but if word
access is executed in the register, for the word area, disregarding the bottom 2 bits of
the address, halfword access is performed twice in the order of lower, then higher.
3. For registers in which byte access is possible, if halfword access is executed, the higher
8 bits become non-specific during the read operation, and the lower 8 bits of data are
written to the register during the write operation.
4. Addresses that are not defined as registers are reserved for future expansion. If these
addresses are accessed, the operation is undefined and not guaranteed.
CHAPTER 3 CPU FUNCTION
x3FFEFFFH
Internal RAM
x3FFE000H
x3FFFFFFH
Internal peripheral I/O
x3FFF000H
User's Manual U12688EJ4V0UM00
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