NEC V850E/MS1 UPD703100 User Manual page 443

DMARQ0 to DMARQ3.............................................. 49
DRAM access ........................................................ 143
DRAM access during DMA flyby transfer ............... 151
DRAM connections ................................................ 137
DRAM controller..................................................... 136
DRAM configuration registers 0 to 3 ...................... 139
DRAM type configuration register .......................... 142
DRC0 to DRC3....................................................... 139
DRST ..................................................................... 173
DS .......................................................................... 168
DSA0 to DSA3 ....................................................... 163
DTC........................................................................ 142
DTFR0 to DTFR3 ................................................... 171
DWC1, DWC2 ........................................................ 113
DWn0 to DWn2 (n = 0 to 7).................................... 113
[E]
EBS0, EBS1........................................................... 290
Edge detection function.................................. 208, 220
ECLR10 to ECLR15 ............................................... 254
ECR ......................................................................... 72
EDO DRAM access timing ..................................... 147
EICC ........................................................................ 72
EIPC......................................................................... 72
EIPSW ..................................................................... 72
Element pointer ........................................................ 71
EN0 to EN3 ............................................................ 170
ENTO1n0, ENTO1n1 (n = 0 to 5)........................... 260
EP ............................................................................ 73
ESmn0, ESmn1 (m = 0 to 5, n = 0 to 3) ................. 221
ESN0...................................................................... 208
ETI10 to ETI15 ....................................................... 257
Example of DRAM refresh interval ......................... 155
Example of interval factor settings ......................... 155
Exception trap ........................................................ 225
External bus cycle during DMA transfer ................. 189
External expansion mode......................................... 87
External interrupt mode registers 1 to 6 ......... 220, 261
External I/O interface ............................................. 125
External memory area.............................................. 86
External ROM interface.......................................... 125
External trigger mode............................................. 325
External wait function ............................................. 114
[F]
FDW....................................................................... 174
FDW0 to FDW7...................................................... 174
FE0, FE1................................................................ 291
APPENDIX C INDEX
FECC ....................................................................... 72
FEPC ....................................................................... 72
FEPSW .................................................................... 72
Flash memory ........................................................ 413
Flash memory programming mode .................. 74, 419
Flyby transfer ......................................................... 185
Flyby transfer data wait control register ................. 174
FR2 to FR0 ............................................................ 320
Frequency measurement ....................................... 279
[G]
General-purpose registers ....................................... 71
Global pointer........................................................... 71
[H]
Halfword access..................................................... 110
HALT mode............................................................ 238
High-speed page DRAM access timing.................. 143
HLDAK ..................................................................... 57
HLDRQ .................................................................... 57
HV ......................................................................... 64
DD
[I]
ID ............................................................................. 73
IDLE ....................................................................... 237
IDLE mode ............................................................. 240
Idle state insertion function .................................... 117
Idle state insertion timing ....................................... 118
IFCn5 to IFCn0 (n = 0 to 3) .................................... 171
Illegal op code definition......................................... 225
Image ....................................................................... 77
IMS1n0 to IMS1n3 (n = 0 to 5) ............................... 255
In-service priority register....................................... 218
Initialization ............................................................ 410
INIT0 to INIT3 ........................................................ 170
INTC....................................................................... 199
Internal block diagram.............................................. 35
Internal peripheral I/O area ...................................... 85
Internal peripheral I/O interface.............................. 107
Internal RAM area.................................................... 85
Internal ROM area ................................................... 80
Internal ROM area relocation function...................... 84
Interrupt control register ......................................... 216
Interrupt latency time.............................................. 229
Interrupt stack pointer .............................................. 71
Interrupt source register ........................................... 72
Interrupting DMA transfer....................................... 192
Interrupt/exception processing function.................. 199
User's Manual U12688EJ4V0UM00
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