Transfer Types; Two-Cycle Transfer - NEC V850E/MS1 UPD703100 User Manual

6.6 Transfer Types

6.6.1 Two-cycle transfer

In two-cycle transfer, data transfer is performed in two-cycles, source to DMAC then DMAC to destination.
In the first cycle, the source address is output to perform reading from the source to DMAC. In the second cycle,
the destination address is output to perform writing from DMAC to the destination.
Figure 6-7 shows examples of two-cycle transfer.
Note that caution is required when in two-cycle transfer. For details, refer to 6.19 Precautions.
BCU states
TI TI
DMAC states
CLKOUT
DMARQn
Internal DMA
request signal
DMAAKn
TCn
A0 to A23
D0 to D15
DRAM area
CSj/RASj
SRAM area
CSk/RASk
BCYST
RD
OE
WE
UWR/UCAS
LWR/LCAS
IORD
IOWR
WAIT
Remarks 1. The circles indicate the sampling timing.
2. Broken lines indicate high impedance.
3. n = 0 to 3
j = 0 to 7, k = 0 to 7 (However, j ≠ k.)
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
Figure 6-7. Timing of Two-Cycle Transfer (1/4)
(a) Block transfer mode (SRAM → → → → DRAM)
T1 T2
TI TI T0 T1R T2R
Address
Data
User's Manual U12688EJ4V0UM00
T1 T2 T3 T1 TW
T1W T2W T2W T1R T2R
Row
Column address Address
address
Data Data
T2 TO1 TO2
T2R T1W T2W TE TI
Column address
Data
181