NEC V850E/MS1 UPD703100 User Manual page 236

Table 8-1. Clock Generator Operation by Power Save Control
Clock Source
PLL mode Oscillation by
resonator
External clock
Direct mode
{: Operating
×:
Stopped
Released by RESET, NMI input
Software STOP mode setting
Software STOP mode
236
CHAPTER 8 CLOCK GENERATOR FUNCTIONS
Power Save Mode
(During normal operation)
HALT mode
IDLE mode
Software STOP mode
(During normal operation)
HALT mode
IDLE mode
Software STOP mode
(During normal operation)
HALT mode
IDLE mode
Software STOP mode
Figure 8-1. Power Save Mode State Transition Diagram
Normal operating mode
IDLE mode setting
User's Manual U12688EJ4V0UM00
Oscillator PLL
(OSC) Synthesizer
{ {
{ {
{ {
× ×
×
{
×
{
×
{
× ×
× ×
× ×
× ×
× ×
Released by RESET, NMI input
or maskable interrupt request
HALT mode setting
Released by RESET,
NMI input
IDLE mode
Supply of Supply of
Clock to Clock to the
Internal CPU
Peripheral I/O
{ {
×
{
× ×
× ×
{ {
×
{
× ×
× ×
{ {
×
{
× ×
× ×
HALT mode